CMOS Gate length: 130nm drawn, 130nm effective
Deep Nwell and Deep Trench Isolation
Double Vt transistor offering (Low Leakage , High Speed)
Dual gate oxide (1.2V for core and 2.5V for IO)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic
TP @ 1.2V: 240/310uA/mic
Bipolar SiGe transistors: High Speed NPN
Typical beta (for 2 families above): 1000/1000
Typical Ft (for 2 families above): 230/150GHz
Power supply 1.2V
Temperature range: -40°C to 125°C
6 Cu metal layers
Low k inter-level dielectric
Standard cell libraries (more than 180kgates/mm2)
Embedded memory (Single port RAM).
Internet of Things, Wearable • Ultra-low-voltage operation • FBB optimizes power/performance • Efficient RF and analog integration Automotive • Well-managed leakage in high-temperature environments • High reliability thanks to highly-efficient memories Networking Infrastructure • Energy-efficient multicore • Adapt performance & power to workload via FBB • Excellent performance in memories Consumer Multimedia • Optimized SoC integration (Mixed-signal & RF) • Energy-efficient SoC under all thermal conditions • Optimized leakage in idle mode
DESIGN KIT VERSION:
FRONTEND BACKEND TOOLS:
Cadence IC 6.1.7
Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight)
Calibre (Mentor Graphics) PVS (Cadence)
PARASITICS EXTRACTION TOOLS:
StarRCXT (Synopsys), QRC (Cadence)
PLACE ROUTE TOOLS:
Innovus (Cadence), ICC (Synopsys)
CORE cells Libraries: – CORE: General purpose core cells – CLOCK: Buffer cells for clock tree synthesis – PR: Place and route filler cells IO cells Libraries: – 1.8V Digital IOs – 1.0V, 1.8V, 3.3V Analog IOs – Body Bias supply pads – Bonding pads and Flip-Chip pads
On request: – SHIFT: Level Shifters libraries – CORI: Isolation cells – CORR: Retention cells – Compensation cells – DLL, PLL.
Typical leadtime: 24-32 weeks from MPW run deadline to packaged parts
STANDARD price in Euro
Area = X*Y including scribe-line.
Price for Area ≤ 2mm² with minimum charge of 1.25mm² including scribe-line.
Special additional discount for CNRS Institutions: 1500€/project
18000+[(Area-2) x 6750]/mm²
Price for 2mm² < Area < 10mm² including scribe-line. Contact CMP when Area is larger.
EP DISCOUNT price in Euro/project
(applied to EUROPRACTICE MEMBERS registered)
Technologie ST 28nm FD-SOI en accès réguliers garantis et à bas coûts dans le cadre de Nano2022 IPCEI, Jérémy Perret, CMP Slides to FD-SOI Aug-15: Andreia Cathelin, ST: ST_FDSOI_analogFocus_ACathelin Oct-13: David Jacquet, ST: st_shanghai_soi_summit_oct_13 Sep-13: Philippe Flatresse, ST: UTBB-FDSOIDesign_Migration_Methodology Order Forms Design submission Press article 12-Mar.-18 by Adele HARS, ASN Outstanding 28nm FD-SOI Chips Taped Out Through CMP
Since 2015, CMP offers several training sessions to the users community. Read more Next training session A two-day training Org.