CMP distributes Design-Kits (DKs), containing principally standard cell libraries, models for specific software tools and design rules.
CMP handles more than 40 design-kits, corresponding to IC’s, Photonic IC’s or MEMS technologies from different foundries.
DK are delivered after signature of a NDA/CLA and on condition that the designs are submitted to CMP for fabrication. Users are informed by CMP when a new DK release is issued, they can update their version.
CMP supports the customers through a DK Support center interface.
The following table always includes current releases. More details in each technology of the Process Catalog:
| Foundry | Process | Frontend Backend tools | Version | Notes |
| ams | IC 0.35um BARC C35B4OA | Cadence IC 6.1.6 | 4.10 ISR15 | Nov.-17 |
| ams | IC 0.35um CMOS C35B4C3 | Cadence IC 6.1.6 | 4.10 ISR15 | Nov.-17 |
| ams | IC 0.35um CMOS/Flash/EEPROM C35B4E3 | Cadence IC 6.1.6 | 4.10 ISR15 | Nov.-17 |
| ams | IC 0.35um ARC C35B4O1 | Cadence IC 6.1.6 | 4.10 ISR15 | Nov.-17 |
| ams | IC 0.35um RF C35B4M3 | Cadence IC 6.1.6 | 4.10 ISR15 | Nov.-17 |
| ams | IC 0.35um HV CMOS H35B4D3 | Cadence IC 6.1.6 | 4.10 ISR15 | Nov.-17 |
| ams | IC 0.35um SiGe BiCMOS S35D4M5 | Cadence IC 6.1.6 | 4.10 ISR15 | Nov.-17 |
| STMicroelectronics | IC 130nm CMOS HCMOS9GP | Cadence IC 5.1.41_USR6 | 9.2 | |
| STMicroelectronics | IC 130nm CMOS HCMOS9A | Cadence IC 6.1.6 | 10.7 | July 2016 |
| STMicroelectronics | IC 130nm CMOS H9SOI-FEM | Cadence IC 5.1.41_USR6, Cadence IC 6.1.6 | 14.1 | |
| STMicroelectronics | IC 130nm CMOS BiCMOS9-MW | Cadence IC 6.1.6 | 2.9.b | April 2017 |
| STMicroelectronics | IC 65nm CMOS CMOS065 | Cadence IC 6.1.6 | 5.4 | |
| STMicroelectronics | IC 55nm BiCMOS SiGe BiCMOS055 | Cadence IC 6.1.7 | 2.8a | July 2018 |
| STMicroelectronics | IC 28nm FDSOI CMOS28FSOI | Cadence IC 6.1.7 | 1.0a | August 2018 |
| STMicroelectronics | IC 160nm BCD BCD8sP | Cadence IC 6.1.6 | 2.4 | |
| STMicroelectronics | IC 160nm BCD BCD8s-SOI | Cadence IC 6.1.7 | 2.1 | |
| STMicroelectronics/IRT Nanoelec/LETI-CEA | IC 130nm CMOS HCMOS9A/MAD200v3 | Cadence IC 6.1.7/Addon NVM H9A@2018.2 | 10.9/2018-4.1 | |
| IRT Nanoelec/LETI-CEA | IC Si310–PHMP2M | Cadence IC 6.1.6 | 2018.1 | |
| MEMSCAP | PolyMUMPS | Cadence | 1 | |
| Tanner | 1 | |||
| Mentor Graphics | 1 | |||
| MEMSCAP | SOIMUMPS | Cadence | 1 | |
| Tanner | 1 | |||
| Mentor Graphics | 1 | |||
| MEMSCAP | PiezoMUMPS | Cadence 5.1.41 | 1.0 | 1 |
| Cadence 6.1.5 | 1.0 | 1 | ||
| Tanner | 1.0 | 1 | ||
| Bulk Micromachining | ams | Cadence 6.1.6 | 4.10 ISR15 | Nov.-17 |
| + Post process | Tanner | 1 |
Notes:
1. Design rules, technology files, DRC
Procedure
To receive the Confidentiality Agreements and/or design kit or documentation distributed by CMP, fill in the Design-Kit request.
Delivery
NDA/CLA and next the Design Kit/Documentation, are sent by one month (time for Foundries agreements to be approved and for the export licence, necessary for non EC countries).
Price
Free of charge for all designed circuits fabricated through CMP runs. Full information is sent in the first signed document named “Confidentiality and Licence Agreement”.
TWO original forms of the Confidentiality Agreements are mandatory.
Design Kit Support Center
A dedicated interface to technical support is available on a secure web site. Several support levels are addressed (e.g. installation issues, use of the technology files or libraries, design-flow, etc.) through different tickets.
Support center
