Outstanding 28nm FD-SOI Chips Taped Out Through CMP
March, 12 2018: ST Fellow Dr. Andreia Cathelin gave a terrific presentation at the recent CMP
As Dr. Cathelin said, this lets ST show their industrial clients just how good the technology is. The chips she chose to cover in her presentation get “spectacular performance”, she said, especially for low-power or power-sensitive SoCs.
by Adele HARS, Advanced Substrate News (ASN)
Executive Viewpoint: Inside a Multi-Project Wafer Program for 3D Integration
April 17, 2015: Multi-project wafer (MPW) programs have long been considered an economical way to integrate different IC designs from various teams to produce IC design prototypes and low volumes. Because IC fabrication costs are extremely high, it makes sense to share mask and wafer resources in this way. MPWs were historically used for 2D designs, but in 2009, Tezzaron Semiconductor launched an MPW for DARPA to develop 3D logic devices that would then be integrated with a Tezzaron DRAM to create a hybrid memory/logic 3D-IC. This was the first MPW to serve 3D integration technologies.
Earlier this year, French institutes IRT Nanoelec and CMP (Circuits Multi-Projets) teamed up to offer an MPW for 3D post-process technologies – a reported industry first as the Tezzaron MPW projects have focused on front-end TSV manufacturing processes to interconnect logic and DRAM. I caught up with Kholdoun Torki, technical director of CMP to learn more about this program, and what it means for furthering the 3D IC cause.