Stud bump bonding interconnections are manufactured at die-level with a Wire- Bonding equipment.

The ball is bonded to the die pad with a gold wire which is then cut right above the ball.

The resulting interconnection allows flip-chip of the die onto a substrate by thermocompression, thermosonic or even reflow process.

Stud bumping does not require UBM or RDL underneath the balls.

Gold stud bumping option is available on any MPW run processed through CMP.

no packaging requested

Micro-Bumps (also called copper pillars) are manufactured at wafer-level as a post-process within CEA LETI cleanroom.

This interconnection is composed of a pillar of copper upon which a Sn/Ag alloy is deposited to ensure electrical contact.

This technique allows very fine pitch (down to 50 µm) and offers improved electro migration performances compared to solder bumps.

The process is the following: Seed Layer (or UBM) deposition, Copper electro-deposition (requires masking), Sn/Ag alloy deposition, Seed layer etching and reflow.

This post-process is available for projects and wafers processed through CMP.

Guaranteed minimum delivered pieces: 40.

OPEN 3D Micro-Bumps post-process option is available as an MPW on the last CMP runs of the year on selected technologies nodes and are subject to a minimum participation.

Diameter and height are set to 25µm/20µm with a 50 µm minimum pitch.

Compatible technologies are: ams C35B4M3, ST CMOS065, ST CMOS028, ST BiCMOS9MW, ST BiCMOS055.

Dedicated run for OPEN3D Micro-Bumps post-process are available on any CMP runs (upon feasibility study).

Diameter/height pair is not imposed and can be chosen within process window.

OPEN 3D post-process must be anticipated at an early stage of the project as they require an additional NDA, the distribution a specific DRM and an add-on to the Design-Kit.

You must indicate it in the reservation form.

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :36

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :40

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :32

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :44

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :48

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :56

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :64

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :52

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :80

Quad Flat Non Leaded (QFN) Thermal performance.

Max 80 I/Os 25; theses packages need thinned dies to 250µm; lids must be sealed; subcontractor Nb of pins :88

Small Outline (SOIC) Max 28 I/Os.

Surface-mount device, rectangular, with smaller outline compared to a DIL package.

Nb of pins :8

Small Outline (SOIC) Max 28 I/Os.

Surface-mount device, rectangular, with smaller outline compared to a DIL package.

Nb of pins :16

Small Outline (SOIC) Max 28 I/Os.

Surface-mount device, rectangular, with smaller outline compared to a DIL package.

Nb of pins :20

Small Outline (SOIC) Max 28 I/Os.

Surface-mount device, rectangular, with smaller outline compared to a DIL package.

Nb of pins :24

Small Outline (SOIC) Max 28 I/Os.

Surface-mount device, rectangular, with smaller outline compared to a DIL package.

Nb of pins :28

C-leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :16

C-leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :20

C-leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :28

C-leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :32

C- leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :44

C-leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :48

C-leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :68

C-leadless Chip Carriers (CLCC) Square surface-mount ceramic package with noleads.

Flat metal contacts are on the 4 sides of the package bottom.

Nb of pins :84

J-Leaded Chip Carriers (JLCC) Square surface-mount ceramic package with J-formed leadsaround its periphery.

The compatible plastic equivalent is PLCC.

Nb of pins :28

J-Leaded Chip Carriers (JLCC) Square surface-mount ceramic package with J-formed leadsaround its periphery.

The compatible plastic equivalent is PLCC.

Nb of pins :44

J-Leaded Chip Carriers (JLCC) Square surface-mount ceramic package with J-formed leadsaround its periphery.

The compatible plastic equivalent is PLCC.

Nb of pins :52

J-Leaded Chip Carriers (JLCC) Square surface-mount ceramic package with J-formed leadsaround its periphery.

The compatible plastic equivalent is PLCC.

Nb of pins :68

J-Leaded Chip Carriers (JLCC) Square surface-mount ceramic package with J-formed leadsaround its periphery.

The compatible plastic equivalent is PLCC.

Nb of pins :84

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins :8

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins :14

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins :16

Thin Quad Flat Pad (TQFP) 25 samples minimum.

Theses packages need thinned dies to 250µm, lids must be sealed.

Nb of pins :32

Thin Quad Flat Pad (TQFP) 25 samples minimum.

Theses packages need thinned dies to 250µm, lids must be sealed.

Nb of pins :44

Thin Quad Flat Pad (TQFP) 25 samples minimum.

Theses packages need thinned dies to 250µm, lids must be sealed.

Nb of pins :52

Thin Quad Flat Pad (TQFP) 25 samples minimum.

Theses packages need thinned dies to 250µm, lids must be sealed.

Nb of pins :64

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :68

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :84

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :100

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :120

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :144

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :160

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :180

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :208

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :224

Pin Grid Arrays (PGA) Up to 256 pins (up to 352 pins on request).

Nb of pins :256

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request Nb of pins :20

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :64

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :68

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :80

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :84

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :120

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :128

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :100

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :144

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :160

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :240

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :256

CerQuad Flat Pack (CQFP) Until 256 I/Os.

Default option is pins bent in gull wing.

J-Leaded pins on request.

Up to 256 I/Os Available options for pins: - Z: gull wing - J: Jleaded - F: Flat.

Default option is pins bent in gull wing.

Nb of pins :208

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins: 28

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins: 18

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins: 20

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins: 24

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins: 40

Dual-in-line (DIL) DIL package is one of the most mature IC pacakges.

It is rectangular with extended leads on the 2 long sides.

(Not recommended for RF or high speed applications).

Nb of pins: 48