ONSEMICONDUCTOR

IC 0.35µm ONC35-I3T25U

Next run : 2021-07-01

TECHNOLOGY CHARACHTERISTICS:

Met. layer(s): 4, thick top metal
Poly layer(s) : 2
Available I/O : I/O standard cell libraries for core and pad limited designs
Temp. range : -40°C/+155°C
Supply voltage : 3.3V/12V

    SPECIAL FEATURES:

    25V HV technology

    APPLICATION AREA:

    Answer to the need for increased digital content in a mixed signal and/or high voltage environment
    3 and 5 metal layers options (thick top metal)
    Additional options on request: HIPO, MiM capacitor, Epi

    DESIGN KIT VERSION:

    1.42p2 (Jul.-20)

    FRONTEND BACKEND TOOLS:

    Cadence IC 6.1.7

    SIMULATION TOOLS:

    Analog simulations: Spectre (Cadence), Eldo (Mentor Graphics – Siemens EDA), Hspice (Synopsys) Digital simulations: Incisive (Cadence)

    VERIFICATION TOOLS:

    Calibre (Mentor Graphics – Siemens EDA)

    PARASITICS EXTRACTION TOOLS:

    Calibre xRC (Mentor Graphics – Siemens EDA)

    PLACE ROUTE TOOLS:

    Synopsys Apollo, Astro and Cadence Silicon Ensemble

    LIBRARIES:

    For standard cell :
    - ultra high density core shell
    - core cell level shifters

    For standard I/O :
    - fat pad I/O library (for core limited designs)
    - tall pad I/O library (for pad limited designs)

    MEMORY OPTIONS :

    Synchronous high speed/high temp single port SRAM
    Synchronous high speed/high temp dual port SRAM
    Low power synchronous SRAM
    Synchronous high speed/high temp diffusion ROM
    Low power synchronous via programmable ROM
    One-Time Programmable (OTP)
    EEPROM (no additional masks or processing steps)

    TURNAROUND TIME:

    18 weeks

    CONTACT 


    Support:

    Estimate request:

    Ask for Design-Kits (DK):
    Request form

    DOCUMENTATION

    Synopsys Design Compiler and Cadence Verilog (for digital design) ; Cadence DFII (4.4.6) and Spectre (for analog design)

    Spectre, Eldo and HSpice (analog simulation)

    Mentor Calibre