An 11GS/s 9-bit DAC produced in 28nm FDSOI which uses two-times interleaving to improve dynamic performance. It contains two sub-DACs which alternatingly perform a conversion. Once a sub-DAC is stabilized it is connected to the output, isolating the output from most transient/settling errors. This is combined with quad-switching which reduces code dependent errors on the supply to boost performance further.
The design demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI technology. Variability and leakage reduction strategies were used to achieve a state-of-the-art low energy performance of 0.17pJ/operation at 35MHz with a supply voltage of 250mV and a back-gate bias of 0.5V. The design was functional down to 210mV. Measurements have shown the trade-off between back-gate bias and voltage scaling.
A 2.8-to-5.8 GHz VCO designed in 28nm UTBB FD-SOI CMOS process adopts a reconfigurable active core to save power and to enable a trade-off between power consumption and phase noise. The CMOS process is instrumental to achieve a tuning range in excess of one octave at low power consumption, while the use of an 8-shaped tank coil yields a VCO that is highly insensitive to external magnetic fields. The VCO operates from 0.9V and has a figure-of-merit of 186-189 dBc/Hz, depending on the oscillation frequency and the configuration of the oscillator core. The active area of the VCO is 380 um x 700 um.
The Smart Wire sensor node is designed to operate in 0.5V supply and was fabricated on 65nm CMOS process. The node is expected to be reliable against 0C to 100C temperature variation, as much as 10% supply voltage ripple, and across different process corners. The integrated sensor node consists of 8-bit temperature and current data acquisition, BPSK modem and data processing, and power line communication modules capable of perpetual operation through built-in energy harvesting, regulation, and fine-grained power management.
EFPGA features a custom dynamically reconfigurable FPGA logic fabric. This regular programmable structure of operators offer the possibility to manage the placement of virtual tasks and to move and reshape these on the FPGA matrice in one clock cycle. This chip is closely related to the FlexTiles FP7 project.
A class-D DCO with LDO has been designed in STM 65nm CMOS process. The oscillation frequency is tunable between 3.0 GHz and 4.3 GHz, with a fine frequency step below 3 kHz and a fine frequency range of 10MHz (both measured at 3 GHz). Drawing 9.0mA from a regulated 0.4V (corresponding to an unregulated supply voltage of 0.6 V), the phase noise is -145.5 dBc/Hz at a 10MHz offset from a 3.0 GHz carrier. The resulting FoM is 189.5 dBc/Hz, and varies less than 1 dB across the tuning range. The FoM increases to above 190 dBc/Hz when the regulated supply voltage is 0.5V. The core area is 850um x 410 um.
An 8.8GS/s 9-bit DAC produced in 65nm CMOS which uses two-times interleaving to improve dynamic performance. It contains two sub-DACs which alternatingly perform a conversion. Once a sub-DAC is stabilized it is connected to the output, isolating the output from most transient/settling errors. This is combined with quad-switching which reduces code dependent errors on the supply to boost performance further.
This is a fully parallel Content Addressable Memory with an automated background checking (ABC) scheme. The proposed ABC scheme continuously tracks the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the 5.5? power reduction of compared with the conventional ML design. Its average energy consumption is 0.77 fJ/bit/search at 1.2V/500 MHz.
This chip includes a mixed-mode delay-locked loop based frequency synthesizer. The circuit generates two independent output tones below 3GHz, and features very low jitter and fast frequency switching. Both analog and digital design flows were applied in the design, and the experimental results agree well with the simulations.
Mixer-first receiver with an on-chip balun in 65-nm CMOS. A second differential-input receiver is included and combined with a wideband blocker detector based on an undersampling converter. The two receivers support different input impedance levels.
The chip includes wideband mixer-first and programmable LNA-based RF front-ends. Both front-ends share the same I/Q-baseband paths. The chip and both receiver chains are designed to exploit high-quality in-package passives.
The Smart Wire sensor node is designed to operate in 0.5V supply and was fabricated on 65nm CMOS process. The node is expected to be reliable against 0C to 100C temperature variation, as much as 10% supply voltage ripple, and across different process corners. This chip is made up of independent blocks meant for preliminary testing and verification purposes. The different blocks consist of 8-bit temperature and current data acquisition, BPSK modem and data processing, and power line communication, and energy harvesting modules.
The RadHard circuit is dedicated to the test of various sensors and memory elements designed to cope with radiation-induced effects (the so-called single event transients and upsets). It embeds various designs of bulk built-in current sensors, which purpose is to monitor the bulk currents induced during such events. Several architectures of radiation-hardened SRAM cells are also embedded. A pulsed laser (1064 nm) will be used to evaluate the hardness of these designs. Tests in a cyclotron are also envisaged.
The Orthogonal-Frequency-Division-Multiplex-Transmitter-IC (OFDM-Tx- IC) is for optical coherent IQ-data transmission for next generation optical core networks with data rates of up to 256 Gbit/s. The OFDM-Tx- IC consists of a Digital Signal Processor (DSP) and two Digital-to- Analogue Converters (DAC). The DSP has real-time inputs and PRBS- generators for real-time 256-IFFT with up to 8 bit per symbol (256-QAM) and subcarrier. Further features are: Zero padding, configurable guard length with cyclic postfix insertion, clipping, spectral shaping and pilot tone insertion. The DAC has a sampling rate of 32 GS/s with 8 bit nom. resolution. The IC is implemented in ST 65 nm CMOS technology.
Technology scaling is leading to supply voltage reduction and shrinking voltage headroom, making it very challenging for analog circuits to achieve high Signal-to-Noise-and-Distortion ratios (SNDRs). To address this issue, we propose Switched-Mode Signal Processing where analog information is represented in terms of pulse widths at the amplifier output stage, which can be replaced with power-efficient rail-to-rail Class-D stages, thus producing Switched-Mode Operational Amplifiers (SMOAs). We have implemented a 0.6V 70MHz 4th order continuous-time Butterworth filter designed with SMOAs that achieves a dynamic range of 58dB, an SNR of 55.8dB and a THD of 60dB at +2.8dBm output signal power, while dissipating 26.2mW.
We propose an ADC architecture based on Switched-Mode (SM) Signal Processing with an integrated rail-to-rail driver. By representing the signal information in multiple binary level signals, SM processing allows fluid transition between multiple signal domains like analog and digital. The resistive-input-driver addresses input and reference buffer issues in traditional architectures and the ADC is resolution and sampling speed-re-configurable. A 6.6mW, 1Vppd full-scale, 100MHz BW prototype with a peak SNDR/DR of 51dB/68dB in the driver and 32dB/53dB in the ADC at 0.6V is achieved.
A new type of neural network called, Encoded Neural Network, is implemented using the ST 65nm CMOS technology. ENNs use feedback loops linking neurons arranged in clusters representing pieces of information to store larger messages. The circuit consists of 30 analogue neurons with 13 synapses arranged in five clusters of six neurons. The neurons are designed using a current- mode approach insuring a low consuming circuit. The implemented ENN includes Power, Voltage and Temperature compensation circuits and is robust to transistor mismatches. The network occupies a surface area of 16500 and consumes only 280fJ to retrieve a stored message on a 1V supply voltage.
The first chip contains a switching-mode power amplifier for broadband operation with a maximum output data rate of 4 Gbps. The CML input interface requires a differential voltage swing of 400 mV. Due to transistor stacking the output voltage is 3V. The second chip contains a 10 bit 90 MS/s asynchronous successive approximation analog-to-digital converter. With a measured effective resolution of 8.8 bit and a power consumption of 1.76 mW, it has a figure of merit of 44.1 fJ/conversion step.
The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.
A 2-dimension Vernier time-to-digital converter (TDC) uses two 3-stage gated-ring-oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (~ 10.6ps) is improved by the 1st-order noise shaping of the GRO. Moreover, since all delay differences between X phases and Y phases can be used (rather than only the diagonal line of the 1-dimension architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC consumes 2.3mA from 1.0V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2ps, while the latency time is less than 1/6 of that in a standard Vernier TDC.
HDG069 is a full custom Phase Locked Loop chip in 0.35um CMOS process. The chip incorporates two different PLL architectures. The PLLs accepts input in the range of 20MHz to 25MHz and provides a low jitter output clock in the frequency range of 400MHz to 500MHz.
This photomultiplier front-end chip embeds 64 parallel channels featuring energy measurement and time stamping in 3.7x8.3 mm2. Each channel has a dynamic input, ranging from 0.3 to 650 photoelectrons. The analogue chain consists of a low noise current mode preamplifier acting as an integrator, a gain corrector compensating the photomultipliers gain variation, a CR-RC shaper reducing out band noise and an analogue memory. The arrival time reference is generated by a current mode comparator. The time stamped in each channel is provided by a reference time unit build around a DLL and a coarse time counter running at 50MHz, the time resolution is 625 ps. The readout is continuous and transfers are performed via a multiplexed analogue output for the energy and a serial digital output for the time.
The configurable interface circuit is designed to have two modes de functionality: temperature reading and pressure reading. The associated sensor has also multi-functionality for : temperature sensing and pressure sensing.
To drive power devices such as GaN HEMT and SiC MOSFET, a special care should be addressed to the design and the packaging of the power switching loop and the gate drivers. These power devices exhibit extremely high dV/dt capabilities introducing great challenges with respect to EMI. It is therefore critical to minimize conducted and radiated propagation paths. In this context, we introduce an integration approach to transfer the gate information and to realize the signal isolation based on CMOS optical detectors and their associated electronics. A CMOS optical isolator, including a light-sensitive detector with its signal processing circuit for gate driver is proposed. This circuit is developed using standard 0.35?m CMOS technology. The optical detectors demonstrated DC responsivitivies between 0.04A/W and 0.32A/W at 1V reverse bias and transient behaviors compatible with our application.
The DBS system used in patients consists of three components: the lead, the extension, and the neurostimulator. The Neurostimulator can be monophasic or biphasic (power consumption and reduction of the board?s total area optimisation). The prototype satisfies all requested specifications (size, consumption, amplitude & frequency) in all technological corners due to a amplitude and frequency trimming. The prototype is the first full integrated electrostimulation system.
This circuit is a low power True Random Number Generator (TRNG), based on the discrete time-chaos, intended for a RFID security applications, to be developped on CMOS 350nm standard technology. The circuit relies on a discrete time chaotic oscillator to generate patterns to be sampled to get a raw random signal to be debiased by a digital corrector.
A 16 channels front-end IC dedicated to X-ray spectrometry applications has been developed for CdTe detectors. It includes, for each channel, an ac coupled device, a low noise density (2nV/Hz1/2), high transconductance (10mS) charge amplifier with three switchable capacitors, allowing three measuring ranges 6fC, 24fC and 72fC. Each channel is designed to accept up to 10pF detector capacitance. The charge amplifier output with 1µs shaping time is directed either to a comparator outputting a pulse above a common reference voltage or a transconductance amplifier with a common mode voltage output and two differential outputs that are able to drive 50Ohm terminations. Each detector input is ac coupled and accepts positive or negative currents up to 25nA. The input common polarity is externally selectable. A summing channel adds the output signals issued from the 16 charge amplifiers. The consumption is about 10mW per channel with a 3.3V supply. The area is 9x20mm2
Ultimate2-Mimosa28 is a CMOS pixel sensor produced for the PXL detector, a part of the Heavy Flavor Tracker of the STAR experiment running at BNL, NY-USA. This ~4 cm² device of ~1 Mpixels, provides a ~3.5 µm spatial resolution on the particle impact. The sensor, designed in C35B4O1 on high-res epi wafers, is edgeless thanks to AMS DRIE technics and is thinned down up to 50 µm. 100 wafers have been produced for successive PXL detectors. The picture shows a ½ detector constructed by LBNL, CA-USA. PXL has a 0.16 m² sensitive area, i.e. 400 sensors, ~360 Mpixels, the readout speed is ~5 kframe/s. PXL is the 1rst tracker based on CMOS pixel sensors ever built for particle physics.
The circuit is composed by 10 independent power inverter legs integrated in the same die with their associated gate driver circuits. It is designed for applications up to 10W and above 1MHz depending on thermal capabilities of the package and the assembly. The power die is designed with respect to the standard PCB design rules for a flip chip assembly. The result is a significant downsizing of chip package, reducing the parasitic phenomena such as interconnect resistances and inductances.
This chip is an integrated and versatile energy conversion solution for battery management applications. It contains multiple power converters that include also embedded intelligence elements. The chip was designed with the 0.35µm CMOS high voltage (20-50V) technology from Austria Microsystems (ams).
SHIVA (Stimulator with High voltage compliance for In Vivo/vitro Applications) is an ASIC designed to provide current mode electrical stimulation of biological tissues in different contexts. The design principle is based on a scale effect on electrode impedances, so that one chip can provide from 1 to 8 channels that can stimulate micro or macro electrode(s). These chip can also be combined to provide stimulation on more than 8 channels setups.
HARDROC3 (HAdronic Rpc Detector ReadOut Chip) is a 64-channel front end chip designed to readout negative fast (<1ns) and short (<10ns) current pulses such as those delivered by the RPC detectors foreseen for the Semi Digital HAdronic CALorimeter (SDHCAL) of the future International Linear Collider. The chip provides a semi-digital readout with 3 thresholds set by 3 integrated 10-bit DACs and tunable between 10fC up to 20pC. An embedded I2C link (designed by IPN Lyon) is used to configure chip parameters. The power consumption is down to 10µW per channel using the integrated power pulsing mode (0.5% duty cycle).
Petiroc2 is a 32-channel front-end ASIC designed to readout Silicon Photomultipliers (SiPM) for particle time-of-flight measurement applications and for any application that requires both time resolution and precise energy measurement. It combines a very fast (GHz) and low-jitter (50 ps) trigger with accurate charge and time measurements which are digitized internally thanks to two integrated 10-bit ADC. A multiplexed charge output is also available as well as the 32 trigger outputs. An adjustment of the SiPM gain is possible using a channel-by-channel input DAC. The power consumption is 6 mW/channel.
The SPACIROC3 ASIC is a 64-channel readout chip for space applications. It is designed for the JEM-EUSO observatory on board of the International Space Station (ISS) to read the 64 channels from MAPMT (multi-anode photo-multiplier). The two main features of this ASIC are the single photon counting for each input and the charge-to-time (Q-to-T) conversion for multiplexed channels. The ASIC data output rate is 100MHz. This chip is radiation tolerant and its power consumption is lower than 1mW/channel.
This ASIC, designed in standard AMS 0.35ùm BiCMOS SiGe technology, is dedicated to the readout and the multiplexing at cryogenic temperature (4.2K) of superconducting bolometer array (24) by using SQUIDs. It includes 8 switching current sources for sequential SQUID biasing, a low noise SiGe amplifier with 3 multiplexed inputs to achieve the SQUID readout and a digital circuit to synchronise the overall circuit. This SQMUX24 ASIC is provided to the Purple Mountain Observatory in the context of collaboration with APC. This circuit will be used for THz astronomy in Dome A (Antartica).
The chip contains a 10x10 network of digitally controlled oscillators coupled through a Cartesian network of all-digital PLLs. This is a second prototype of a network of oscillators coupled in frequency and in phase, intended for generation of a global clock in large digital SOCs, designed in HODISS and HERODOTOS projects funded by ANR. This prototype contains 100 clock generators, each of them are coupled with their immediate neighbours. The oscillators tuning range is 0.9-1.16GHz. The chip contains advanced test devices allowing an on-chipmeasurement of picoseconds phase errors on high frequency signals. The chip is a first experimental proof of distributed synchronization of large networks of CMOS oscillators used with all-digital PLL networks
PAnDA (Programmable Analogue and Digital Array) is a novel FPGA architecture that can be reconfigured at the transistor level, in addition to the digital level. This allows fine-grained, post-fabrication optimisation of mapped designs in order to manipulate the operating-point of the design, mitigate the effects of process variations and improve reliability 47
PAnDA (Programmable Analogue and Digital Array) is a novel FPGA architecture that can be reconfigured at the transistor level, in addition to the digital level. This allows fine-grained, post-fabrication optimisation of mapped designs in order to manipulate the operating-point of the design, mitigate the effects of process variations and improve reliability/fault tolerance. PAnDA Zwei is the second prototype chip fabricated on the EPSRC funded PAnDA project. The aim of the chip is to test revised versions of the mini-CAB and slice components of the PAnDA architecture.
Test and evaluation of a RISC32 processor called SecretBlaze with its memory, Wishbone and FSL buses, peripherals and clock and reset modules. This processor is fully programmable and testable through an ad-hoc JTAG solution.
This is a 3.5 GHz digital FDC-based fractional-N PLL frequency synthesizer that uses a dual-mode ring oscillator in place of a charge pump and ADC, and quantization noise cancellation to achieve spur performance comparable to an analog PLL. Its largest in-band fractional spur is -60 dBc, its reference spur is -81 dBc, and its phase noise is -93, -126, and -151 dBc/Hz at offsets of 100kHz, 1 MHz, and 20 MHz, respectively. Its active area is 0.35 mm2 and it dissipates 15.6 mW from a 1 V supply.
In this work, a capacitive-discharging relaxation based oscillator is implemented that achieves both ultra-low-power and frequency-stable operation without any calibration or external components. The oscillator is able to generate a 2.8Hz clock with sub-nW power consumption.
The design is for high speed LVDS driver for 2.5D Through Silicon Interposer (TSI). A novel equalization scheme in the design is to compensate for the inherent high insertion lost from the TSI strip line. The equalization amount is adjustable covering up to 3 taps while occupying very small footprint, equivalent that of 1 tap, and consuming only small amount of power.
This Chip contains two sigma-deltamodulators (2 and 10 MHz BW) using low power techniques. These new techniques allow the modulators to achieve very high energy efficiency with a dynamic range of 12-bit.
The first chip contains two switching-mode PAs for broadband operation. The CML input interface requires a differential voltage swing of 300 mV. Due to transistor stacking the output voltage is 6V. The amplifiers can be operated independently or in differential mode. The second chip contains a switching-mode PA for broadband operation. The supply voltage for the PA is configurable with an on-chip register and can be set to 1V, 2V or 3V.
The test chip contains circuit blocks necessary to provide low power 2.4GHz wireless communication, 5.8GHz wireless energy harvesting, and power regulating units for the second prototype of the SmartWire sensor node. Themodules are designed for individual performance characterization across process, supply voltage, and temperature variation. The chip is implemented in 65nm CMOS process and the blocks are designed to operate at sub-1V supply.
A multiproject design including:
- A BIST circuit to detect open defects on emulated TSV structures.
- A circuit to analyze power distribution networks. - Defective SRAM arrays to validate test strategies.
- An adaptative flash ADC.
- A probe attempt detector.
- A physical unclonable function.
Description of the circuit: (text of 3 to 10 lines maximum): This work presents a digital calibration technique in CT A/D converters. The converter is clocked at 144MHz with an OSR of 8. Non-idealities in the outermost DAC are measured and removed in the background by digital circuit. Both analog and digital parts are implemented in a single chip.
This is a wideband quadrature radio receiver employing DeltaSigma-based A/D-converting channel-select filters (ADCSFs). The ADCSFs incorporate the functionalities of both channel selection and data conversion in a single power-optimized block. The 65nm CMOS receiver has a frequency range of 0.6–3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths.
A low phase noise cross-coupled VCO with significantly better phase noise performance specially at close-in offset frequencies is presented. It is designed by manipulating the ISF and NMF of the transistors. It has no power or area overhead compared to a conventional one while phase noise is improved by 17dB and 8.2dB at 10kHz and 1MHz offset frequencies. The oscillator achieves a FOM of almost 190dBc/Hz at 10kHz-2MHz offset frequencies referring to a 2.4GHz carrier.
This is a 320-GHz high output power transmitter. In this transmitter, 16 high power radiator cells are locked to an 85-GHz phase-locked loop. This transmitter is designed for a high sensitivity heterodyne terahertz imaging system.
This is a coherent terahertz detector formed by an 8-cell detector cell array. Utilizing the second harmonic, a 170GHz LO is generated by the on- chip phase-locked loop. This detector is designed for a high sensitivity heterodyne terahertz imaging system.
This circuit is dedicated to provide 5 interleaved PWM signals needed to control an isolated low power micro-converter. The originality of the chip consists of the implementation of specific functions such as self- alignment in phase of the carriers and self-balancing of the converter leg currents. This analog version provides PWM signal up to 3MHz.
To drive power devices such as GaN HEMT and SiC MOSFET, a special care should be addressed to the design and the packaging of the power switching loop and the associated gate drivers. These power devices exhibit extremely high dV/dt capabilities introducing great challenges with respect to EMI. It is therefore critical to minimize conducted and radiated propagation paths. An integrated CMOS driver is developed while implementing all the required functions from the integrated optical isolator (including an optical detector and its signal processing circuit) to the power gate charge control and also a floating supply to deliver energy to these systems by light. This approach allows providing a complete power switch module that can be used either as a high side or low side switch.
This circuit represents a SiPM, which is Silicon single photon sensitive device built from an avalanche photodiode (APD) array on common Si substrate. The idea behind this device is the detection of single photon events in sequentially connected Si APDs.
This circuit represents an array of 8x8 SiPMs. This matrix could be used in many applications for Single Photon Avalanche Diode (SPAD) such as astrophysics and biological applications. The idea behind this device is the detection of single photon events in sequentially connected Si APDs.
This circuit represents different components (MOS, APD, SiPM…) for test. This test will be important for definition of many parameters for the optimal MOS transistor for use in APD and SiPM circuits. The association of MOS transistor in series with an APD represents the typical SPAD (Single Photon Avalanche Diode) circuit for integration into SPAD array.
ALPS : Asic de Lecture Pour SiPM Front-End circuit for the readout of a 16 pixels SiPM matrix. The chip contains 16 channels, each including a two gain current mode preamplifier and an 8 bits gain adjustment. The outputs consist in 2 analogue sums of the 16 high and low gain channels. A fast discriminator on the high gain sum with a 10 bits programmable threshold provides a trigger signal. The chip also includes 16 8 bits DACs to adjust each pixel gain and slow control registers.
This 1.8mm x 0.6 mm IC implements a broadband (500MHz-2 GHz) power amplifier with output power above 30 dBm. The circuit achieves high power by using series-connected (stacked) transistors, implemented with S T Micro’s high voltage LDMOS in SOI technology, and leverages the high ft of these devices along with the high resistivity substrate to reduce parasitics. Broadband capability is achieved by the fact that the drain operates directly into 50 ohms without the need for narrow-band matching circuits.
It is a flexible mixed-signal transmitter block for the WiFi wireless communication standard. It implements a filtering digital-to-analog converter that can be configured to realize the transmit mask requirements of 160 MHz mode of the IEEE 802.11ac (5 GHz) and the single carrier mode of the 802.11ad (60 GHz) standards. It occupies an area of 1 mm2.
The design is for a BTI-Aware SRAM. A write wordline (WWL) voltage level control scheme is design to lower the WWL voltage before the half-selected cell stability fail due to BTI degradation. The beneficial of the scheme is it recovers the degraded cell stability without changing any SRAMâââââ€Å¡¬Å¡¬Å¡s initial operating parameters.
A QR Decomposition processor is often used in small scale MIMO systems to enhance performance. The fabricated circuit is an adaptive version of the QRD process, capable of meeting the requirements for 100 MHz Carrier Aggregated LTE-A. The measurement results indicate that forward body biasing can double the operational frequency and a combination of supply scaling and body biasing leads to a reduction of power dissipation for a required throughput.
The fabricated circuit is a flexible 1mm x 1.1mm 128x8 massive MIMO digital processor supporting both precoding and detection. Novel approximative Givens rotation lowered QR decomposition complexity by 50% when employed for precoding. An adaptive detection framework is proposed which supports both linear and non-linear detection. Circuit optimization and utilizing FD-SOI body-bias resulted in measured energy of 6.56 nJ/QRD and 60 pJ/b at 300 Mb/s detection rate.
A 16Gb/s 28nm FD-SOI CMOS receiver for chip-to-chip interfaces. Using a decision feedback equalizer with 1 IIR tap + 1 discrete-time tap and including integrated clock recovery and adaptation, it equalizes a 28dB-loss channel. An edge-based algorithm adapts both the IIR and DT equalizer coefficients using the same high-speed circuitry required for clock recovery.
Achieving wireless communications at 5-30Mb/s in energy-harvesting Internet-of-Things (IoT) applications requires energy efficiencies better than 100pJ/bit. Impulse-radio ultra-wideband (UWB) communications offer an efficient way to achieve high data rate at ultra-low power for short-range links. We propose a digital UWB transmitter System-on-Chip (SoC) designed for ultra-low voltage in 28nm FDSOI CMOS. It features a PLL-free architecture, which exploits the duty cycling nature of impulse radio through aggressive duty cycling within the pulse modulation time slot for high energy efficiency and minimum jitter accumulation. Wide-range on-chip adaptive Forward Back Biasing (FBB) is used for threshold voltage reduction, PVT compensation and tuning of both the carrier frequency and the output power. To ensure spectral compliance with output power regulations without the use of bulky and expensive off-chip filters, a programmable pulse-shaping functionality is integrated in the digital power amplifier based on a 7-9GS/s 5-bit current DAC. Operated at 0.55V, it achieves a record energy efficiency of 14pJ/bit for the transmitter alone and 24pJ/bit for the complete SoC with embedded power management. The transmitter SoC occupies a core area of 0.93mm.
Contacts : Shayan Shahramian, Behzad Dehlaghi, Tony Chan Carusone
emails : email@example.com
Chip I/O bandwidth must increase to take full advantage of tomorrow's highly parallel processors, but the total power available for I/O is constrained. This project sought low-power solutions for high data-rate chip-to-chip communication that are adaptive and, hence, robust over a wide variety of conditions. A mixed-signal 1 IIR + 1 discrete-time tap decision feedback equalizer with integrated clock recovery and adaptation is demonstrated. At 16Gb/s with a 28dB-loss channel, a BER below 1e-12 is measured over a 0.27UI timing window. A novel edge-based algorithm adapts both IIR and DT equalizer coefficients using the same high-speed circuitry and signals required for clock recovery. The adaptive DFE converges within 5us and, unlike past approaches, converges for almost any incoming data statistics.
The basic neuron circuit and organisation of the encoded neural networks are described in .This circuit integrates a single cluster of 128 analogue neurones having each 30 synapses. The goal is to reduce circuit complexity by iterating on this single cluster to build networks having thousands of neurons. Parallelising chips will further increase this network size.
The chip ctsRX_io is a digital pre-processor that is part of a Chirp Transform Spectrometer designed for the space mission JUICE. It contains two ADC's running at 1 GHz, a block for digitally pre-processing the measured data, and RAM for storing and averaging them.
PAnDA (Programmable Analogue and Digital Array) is a novel FPGA architecture that can be reconfigured at the transistor level, in addition to the digital level. This allows fine-grained, post-fabrication optimisation of mapped designs in order to manipulate the operating-point of the design, mitigate the effects of process variations and improve reliability/fault tolerance. PAnDA DreiPunktEins is an updated version of the third prototype chip fabricated on the EPSRC funded PAnDA project. The aim of the chip is to test a complete version of the PAnDA architecture, including the reconfigurable global and modified inter-CAB routing.
PAnDA (Programmable Analogue and Digital Array) is a novel FPGA architecture that can be reconfigured at the transistor level, in addition to the digital level. This allows fine-grained, post-fabrication optimisation of mapped designs in order to manipulate the operating-point of the design, mitigate the effects of process variations and improve reliability/fault tolerance. PAnDA F nf is fifth and final prototype chip fabricated on the EPSRC funded PAnDA project. The aim of the chip is to test a large, scaled-up version of the complete PAnDA architecture, including elements from all the previous PAnDA prototypes.
PAnDA (Programmable Analogue and Digital Array) is a novel FPGA architecture that can be reconfigured at the transistor level, in addition to the digital level. This allows fine-grained, post-fabrication optimisation of mapped designs in order to manipulate the operating-point of the design, mitigate the effects of process variations and improve reliability/fault tolerance. PAnDA Vier is the forth prototype chip fabricated on the EPSRC funded PAnDA project. The aim of the chip is to test a complete version of the PAnDA architecture, including alternative matched widths for the configurable transistors.
This is a full design of digital phase locked loop based digital to time converter and single phase detector. This design introduces digital techniques working in background to achieve high performance in terms of phase noise and spurs for advanced LTE communication
A receiver front end with a tunable notch filter in the baseband. The notch effectively reduces the blocker amplitude resulting in high blocker tolerance. Simulations show that the notch can be effectively tunable down to less than one octave close to the wanted signal.
A highly configurable Rx front end supporting contiguous and intra band noncontiguous CA bandwidth with fully integrated low resolution spectrum analyzer. The spectrum analyzer consists of a high Q fourth order complex band pass filter followed by a power detector and a low pass filter.
Test LSI circuit designed for the examination of the reliability parameters provided by the manufacturing technology. Test structures for superior understanding of 65 nm process and analysis of electronic circuits and patterns. The additional goal is to teach master and undergraduate students of the modern technology features.
The characterization of the STM 65 nm process and the development of the algorithms for readout, collection and processing of the data from sensors. The second version of the Digital IC, supplied by LVDS receiver as an input interface. There are three more test blocks in the chip, namely LVDS transmitter, clock generator and electronic thermometer. Undergraduate students project
This is a full design of digital phase locked loop based digital to time converter (DTC), single phase detector and Class-D DCO. This design introduces digital techniques working in background to achieve high performance in terms of phase noise and spurs for wireless communication systems with fast frequency locking and the ability to fix the nonlinearities introduced in the DTC by means of predistortion technique.
This prototype implements an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram.
We have implemented a 65nm CMOS Epsilon Delta modulator with 94dB Dynamic Range (DR). The power dissipation is 407umW in a 500kHz signal bandwidth under a 1.2V power supply voltage. This design proves that the feedforward Epsilon Delta topology is an excellent topology for low-power, high bandwidth and high resolution Epsilon Delta ADC designs in nm CMOS technologies.
An ultra low voltage VCO-based ADC was designed and taped out using STM65nm technology. The nonlinear Voltage to phase/Frequency relation of VCO results in a nonlinear output. A background calibration scheme was used to estimate and correct nonlinearity. . ADC operates at 0.4V and giving 8.8bits ENOB, over 10KHz bandwidth with a power consumption of 1.15uW.
A novel current reference, which adjusts the bias voltage automatically for any process and temperature variation was designed and taped out. The current source discussed above was used to design a continuous time first order delta sigma ADC with VCO integrator. Current reference is used to set the VCO centre frequency and feedback current DAC current. The design operates at an operating voltage of 0.3V. On Measurement ADC gives 8.7bits resolution over 10KHz bandwidth with a power consumption of 0.5uW.
The ADC can be set for either IQ or II sampling of the two channels. It features per-channel low, mid and high reference inputs for tuning sample levels. The digital outputs have a time division multiplexing factor of four to reduce per-io frequency for the digital autocorrelator. The 17 digital outputs (including clock for autocorrelator ASIC) use differential current-mode signalling. Operating at 3.3 V the power consumption, including IO, is 781 mW. Maximum sample rate is above 16 GHz.
This chip is a chip multi-circuit consisting of several circuits. The circuits are High speed 8-Bits Pipeline Analog Digital Converter (ADC), 4-Bits Single Slope Analog Digital Converter (ADC), Pre-amp Electro Cardio Graph (ECG). Analog Neural Network, 8-Bits DAC For High speed Communication System, and high speed 4-bits Asynchronous ADC.
The chip contains test circuits of two large arrays of MOS transistors (64x64) used to evaluate matching properties of the MOS devices in a wide range of temperatures (4.2 K to 300 K). The chip also has various circuits, such as 2nd-Order Sigma Delta Modulator, Multiplexer, Level shifter, and so on, for test at very low temperature (4.2 K)
RoBo is a prototype designed in AMS CMOS 0.35 ùm. It is made of different types of instance dedicated to the readout of cryogenic bolometers for space applications. This first prototype has been successfully tested at 100 mK. This is the first time that this technology is tested at such a low temperature.
The chip was designed to study transistor characterisations and circuits over the 5-300 K temperature range. The aims of the projects were to develop a cryogenic transistor model and interface circuits for quantum computing developments. The chip consisted of P/NMOS and circuits such as ADC, Op-Amp, Ring Oscillator, etc., arrays, which used to study MOS characteristics and circuit performance at cryogenic temperatures. The outcomes of this research are:
This test-chip includes different Single Photon Avalanche Diodes (SPADs) and their electronics in various configurations (quenching and passive or active recharge electronics) and small arrays (4pixels) and has been especially designed for the experimental measurements of the SPAD performances such as dark count rate, photon detection efficiency, timing jitter.
The chip contains bare transistors (CMOS/SiGe) and test circuits of an array of SiGe transistors (8x16) used to characterise and evaluate matching properties of the devices in a wide range of temperatures (4.2K to 300K). The chip also has various circuits, such as SiGe LNA, VCO, Gilbert Mixer, and so on, for test at very low temperature (4.2K).
The integrated circuit consists of five circuit blocks, including two linear 2-GHz power amplifiers (targeting at 20- and 25-dBm output power) using novel embedded linearizer, two conventional 2-GHz power amplifiers for performance comparisons, and one active component testing module.
Convolutional Neural Networks (CNN) are currently state-of-the-art in visual recognition. Existing CNN platforms are limited to 100's of GOPS/W, which is insufficient for always-on visual processing. This work introduces hierarchical recognition, together with Envision: an energy-scalable ConvNet processor achieving efficiencies up to 10 TOPS/W by modulating computational accuracy, voltage, frequency and the FDSOI body-bias as a function of the network's computational accuracy requirements, all while maintaining recognition rate and throughput. Envision hereby enables always-on recognition in wearable devices.
XTRACT is a 32-channel ASIC developed to meet the requirements of an innovative 3-gamma medical imaging detector based on a liquid xenon camera. Each channel of this chip is mainly composed of a Constant-Fraction Discriminator (CFD) and an analogue-memory, in which time and energy values are stored for each self-triggered event. An Asynchronous Tree-Based Multicasting (ATBM) block controls the write-and-read sequencing, whereas an I2C interface allows the configuration of each channel. The power consumption of XTRACT is limited to 40mW and it is adapted to operates at a temperature of about -100›C
The architecture of ASTRE chip is based on the one of AGET ASIC [Ref 1] with few modifications and layout optimization of the digital part against latch-up. Each of the 64 channels includes Charge Sensitive Amplifier (4 Gains: 120 fC, 240 fC, 1 pC or 10 pC) followed by CR-RC2 shaper (16 peaking time values: 50 ns to 8 ns). The shaped signal is continuously sampled in a 512-cell deep circular buffer (SCA) at a clock frequency which can be set from 1 MHz to 100 MHz. The sampler is stopped on an external trigger decision and the analog memory is read back at a rate up to 25 MHz. Three different readout modes are available: all channels, only hit or specific channels.
This ASIC is dedicated to the readout and the multiplexing of 128 superconducting SQUID devices for astrophysical applications. It has been specially developed for the cosmology experiment QUBIC, a ground based telescope which aims to measure the B-mode polarization of the Cosmic Microwave Background. The ASIC operates at 4.2K and includes the needed multiplexed ultra-low noise amplifiers, switched current sources and digital sequencing circuit.
awaXe_v1 (Athena Warm Asic for the X-ifu Electronic - Version1) is the first generation of an ultra stable gain low noise amplifier (LNA) for the readout chaine of the X-ray Integral Field Unit (X-IFU) instrument of the Athena space observatory. This ASIC also provides current biasing for the SQUID (Superconducting QUantum Inteference Device) pre-amplifier/multiplexer stages. Indeed, the focal plane of the X-IFU instrument is composed of about 4000 cryogenic micro-calorimeters. These sensors, based on superconducting Transition Edge Sensors (TES), are read out through a cryogenic multiplexer. This first version ASIC will be used for validating the ultra stable gain LNA and current sources. Moreover, specific I2C serial protocol has been implemented for biasing adjustment. These digital parts have been developed with a RadHard by Design digital library. The library has been also tested in this awaXe_v1 ASIC.
The abundance of users contributes to strong interference signals, also known as blockers that potentially degrade receiver performance. Beamsteering receivers can filter blockers by combining signals from a phased array; however, the antenna elements in the phased array introduce a distinct delay in the received signals. This delay varies with the reception angle of the beam and position of the antenna element. Accordingly, the received signals sum up constructively, given this delay is compensated for in the time-domain. Moreover, signal paths experience mismatches arising from process tolerances, temperature, power supply variation, aging and other non-ideal effects. In practice, multi-antenna systems, such as the beamsteering receiver, function close to desired behavior after calibration of amplitude and phase mismatches between parallel signal paths. The designed circuit is a beamsteering receiver intended to overcome the existing challenges for commercialization of this architecture. The proposed architecture consists of LNA, mixers, baseband amplifiers, delay line, FFT, test signal generator, switch matrixs and analog-to-digital converter.
Thanks to the high frequency transition and the low current leakage of the FDSOI 28nm, a low-power LNA working in weak/moderate inversion has been realized. This design is based on the gm/ID method to reduce its intrinsic power consumption. In order to benefit from low leakages of this technology, a fast duty cycled LNA and a fast duty cycled LDO have been designed. This design is based on RFPG (RF power gating) technic to achieve an adaptive LNA. The entire system of LDO and LNA RFPG can be turned on in less than 50ns. When applied in the context of the ZigBee standard, a -85dBm sensitivity can be achieved in the RFPG mode and a power reduction of 80% can be reached. PS: This work has been granted by the European Community through the projects THINGS2DO and CONVERGEANCE.
Contacts : Otto Rolloff, Rodrigo P Bastos, Laurent Fesquet
emails : laurent.Fresquet@univ-grenoble-alpes.fr
Body-biasing is a well-known technique for dynamically tuning Vth and, thus trading-off circuit performances for power consumption. In order to fully benefit from body-biasing techniques, tracking unnecessary leakages will further improve the attractiveness of FD-SOI for low-power systems. This can be done by combining biasing schemes with an activity sensing circuitry for reducing leakage consumption during the idle periods. Asynchronous circuits intrinsically embed the ability of sensing activity, thanks to their local synchronization signals. This local signalization is used in this testchip for locally controlling the activation of body-biasing. This circuit embeds multiple body-biased regions in order to analyze energy efficiency with different region areas. Covering from coarse to fine grain regions by adjusting the pipeline depth of chained arithmetical units, this testchip will be exploited for analyzing and giving guidelines to designers interested in low-power body-biased asynchronous systems.
In high-speed mixed-signal circuits, CML logic with passive inductive peaking may not be practical due to the large area required by the inductors. Here, the highest sampling rate SAR ADC lane for use in time-interleaved ADCs for high-speed communication applications is implemented using active peaking CML logic. Active inductors were implemented by connecting a HBT with added base resistor above the resistive load in CML gates. The ADC has 6 bits of resolution, uses a R2R DAC, and a switched emitter follower track and hold amplifier. It is evaluated by converting the resolved digital bits back to an analog signal using an on chip DAC and output buffer. The measured large signal bandwidth was 17.5 GHz. The SAR ADC lane itself consumes 70 mW, while the 40GHz clock generation circuits consume 60 mW. The measured performance at different sampling can be seen in the figure to the right.
The chip is a 4-channel TIA for high-speed optical receivers in (intra/inter-datacenter) optical links (Ref. , ). The chip contains four high-speed transimpedance amplifier channels and measures 3.2x1.2mm. It is intended for low-power NRZ datacenter links above 50 Gb/s. Initial test results have been published at ECOC 2018 (Ref. ), further publications and testing efforts are ongoing.
Mach Zehnder modulators are widely used as optical transmitters for fiber-optic communications. Travelling Wave MZMs integrated on a Silicon Photonic or III-V platform have lead to small, high-speed optical transmitters (Ref. , ). A 4 channel 56 Gbps NRZ driver designed to drive 50 Ohm Travelling Wave MZMs has been designed, ready to be directly connected to such MZMs. The 4 channels can each drive a 50 Ohm Travelling Wave MZM at 56 Gbps (NRZ) with a differential voltage swing of 2 Vpp. Both DC-coupling and AC-coupling between the driver and MZM are possible, allowing several MZM topologies to be used with the driver. If required, biasing the MZM can be done trough the driver. Configuring the voltage swing, additional equalization of the output, line equalization and correction of the eye-crossing can be configured in the driver using the SPI-interface.
Long wavelength radio astronomy observations needs receiver with a minimum dynamic range of 120 dB over 100 MHz bandwidth. This extremely high dynamic range is not achievable with one single A/D converter for the considered bandwidth. In the STAR project we develop a new architecture fully integrated based on stacked A/D converters, where the input signal is split into multipath, each with different fixed gain amplifier before the A/D converter.The output signal is selected from the channel with the largest magnitude without saturation. The architecture hence is able to track a 120 dB dynamic range. The circuit shown on the left is the first step of the receiver design. It represents the implementation of the 90 dB amplification chain. The circuits is 3 fully differential amplifiers cascaded with 30 dB of gain each. The output of each amplifier is fed to the global output via a fully differential buffer. The 3 dB bandwidth of the amplifiers is 1KHz-100MHz. The maximum level input and output signals is 1 Vpp. A single amplifier is also implented in the chip for stand-alone test. For a proper operation a calibration technique is developped that copes with the phase and gain mismatches between channels allowing thereby to reach the minimum required SNR of 30 dB over all the input range.
With the rapid development of information theory and semiconductor technology, there is a growing demand for real-time signal acquisition for receiving signals in the RF and microwave range for next-generation communications, and surveillance applications. From the compressed sensing theory, the signal reconstruction is possible even with a sub-Nyquist sampling frequency by using a random sensing matrix, which satisfies the restricted isometry property (RIP) condition when the input is sparse. We demonstrate an ultra-fast compressed sensing receiver (CSRX) that operates in the microwave range with a 128.5×sub-Nyquist acquisition for detecting multiple unknown signals in the range of 18 GHz by integrating broadband receiving chains with 36Gb/s PRBS generators in STM 0.13-?m SiGe process. The figure below presents 18 GHz FM signal spectrum with a baseband pulse signal, and (b) the sensed and reconstructed IF spectrum for the 18GHz FM input using the implemented CSRX.
he goal of this test vehicle is to validate the functionality and performances of a RRAM-based FPGA. This chip is a 2x2 FPGA using Resistive RAM. In our RRAM FPGA, all the conventional SRAM-based routing multiplexers are now using RRAM devices to routh the datapath signals. In addition, the SRAM configuration circuits of the different LUTs are replaced by non-volatile RRAM-based topology. As such, the FPGA is able to retain its configuration even while being powered-off.
ReASOn is a online learning neuromorphic test-chip featuring 2048 memristive devices in a differential configuration implementing 1024 memory cells[1, 2]. The chip is intended for testing a memristive devices and neuromorphic circuits including an alpha and shunting synapses, hebbian/anti-hebbian learning protocols, and a new neuron circuit.
This test vehicle is intended to test the functionality of a basic FPGA block: a configurable logic block. This CLB is RRAM-based. A CLB is composed of RRAM-based routing multiplexers, a 6-input LUT, several NVSRAMs and a DFF as well as an output multiplexer.
This test vehicle is intended to test the functionality and characterize simple RRAM-based blocks. It contains: 1T1R and 4T1R programming structures as well as several logic blocks: NVDFF, CMOS multiplexers, RRAM-based multiplexers and a CMOS 4-input LUT.
A new type of image sensors has recently been introduced: the event-driven asynchronous image sensors. They are one of the most promising alternatives to the classical image sensors. Its concept is most of the time based on associating the sensor activity to the motion in the scene. In other words, the scene activity triggers the image sensor processing. The pixels of asynchronous image sensors behave as event detectors. In this case, asynchronous pixels trigger the image sensor reading flow. Hence, the asynchronous pixels control the sensor data flow according to the scene. Multiple architectures of our event-driven asynchronous pixel are embedded in this testchip. This circuit will be tested in order to validate our perspective and thus leading to the fabrication of the event-driven image sensor prototype.
A new type of image sensors has recently been introduced: the event-driven asynchronous image sensors. They are one of the most promising alternatives to the classical image sensors. Its concept is most of the time based on associating the sensor activity to the motion in the scene. In other words, the scene activity triggers the image sensor processing. The pixels of asynchronous image sensors behave as event detectors. In this case, asynchronous pixels trigger the image sensor reading flow. Hence, the asynchronous pixels control the sensor data flow according to the scene. Multiple architectures of our event-driven asynchronous pixel are embedded in this testchip. This circuit will be tested in order to validate our perspective and thus leading to the fabrication of the event-driven image sensor prototype.
The cardiovascular diseases are the leading cause of death around the word. An accurate estimation of the heart rate variabilty allows to detect/prevent abnormal EKG signals. This chip has been designed to detect the energy contained in an EKG signal in order to detect the occurrence of heartbeats. Among the bookstores proposed in this technology, we used the process-related libraries HV CMOS AMS 0.35µm at 4 levels of H35B4S1 metals: CORELIB, A-cells, PRIMLIB and AnalogLib. This chip contains an analog multiplier (Gilbert cell), an integrator and a comparator. The main objective was to achieve a Nonlinear Energy Operator (NEO) which detects heartbeat in a noisy EKG signal. At the NEOs output an integrator has been connected in order to filter the high frequencies contained in the signal. Finally, in order to detect spikes of interest a AOP-based comparator was also designed to set a threshold and acts as a decision block stage. The results obtained are very satisfying and are very similar to those obtained in the post-layout simulations. The esults of the full energy detector which integrates also some Matlab post-processing functions show a detection rate about 89.1% for SNR upper than 0dB and a 100% rate for SNR upper than 6dB.
PET imaging, SIPM electronics readout.This photomultiplier front-end chip embeds 16 parallel channels featuring energy measurement and time stamping in 3.7x4.3 mm2. Each channel has a dynamic input, ranging from 150fC to 1nC charge from photodetectorss. The analogue chain consists of a low noise current mode preamplifier acting as an integrator, a gain corrector compensating the photomultipliers gain variation, a CR-RC shaper reducing out band noise and an analogue memory. The arrival time reference is generated by a current mode comparator. The time stamped in each channel is provided by a reference time unit build around a DLL and a coarse time counter running at 80MHz, the time resolution is 25 ps. The readout is continuous and transfers are performed via a multiplexed analogue output for the energy and a serial digital output for the time.
Frequency-modulated (FM) MEMS gyroscopes promise to overcome all the limitiations of amplitude-modulated (AM) sensors guaranteeing inherently accurate scale factor, improved bias stability, high dynamic range, and low power dissipation. In this framework, a frequency-to-digital converter is needed to acquire the signal coming from the oscillator (coupled to the MEMS gyroscope) and convert it in the digital domain to be processed. This circuit implements a 3th order [sigma delta] frequency-to-digital converter able to sense a single-axis MEMS gyroscope resonating at 25kHz. It is based on a type-II analog PLL with an integreted 2nd order passive filter and a 50-kHz ring oscillator. The analog output is fed to a 20-MHz counter assessing the oscillator period as the difference between two consecutive counts The converter achieves a resolution of 100?Hz in a 100-Hz band for a 25-kHz signal, corresponding to 36 mdeg/s with a maximum input range of 3600 deg/s (100-dB dynamic range) while consuming 250µA at 3.3V. This chip includes also the oscillator coupled to the 25-kHz resonating gyroscope. It consists of a charge amplifier, a 90-deg shifter, a hard-limiter, which implements the non-linear stage required for oscillation build-up, and an H-bridge, which delivers the drive actuation waveforms to the MEMS.
This integrated circuit is dedicated to the readout of superconducting bolometer arrays for astrophysics observations in Dome A (Antarctica) in the framework of collaboration with the Purple Mountain Observatory. It performs, at cryogenic temperature down to 4.2 K, the time-division multiplexing of 4 columns of 32 superconducting SQUIDs devices in series for the readout of 128 TESs. The ASIC includes the needed multiplexed low noise amplifiers, switched current sources for biasing of the SQUIDs and digital addressing circuit for the overall sequencing of the multiplexor.
The chip is designed to do coherent combination required for beam-steering. Two test RF signals are input to the chip with delay between them. The delay is used in the test setup to mimic an antenna structure. The signals are down-converted before combination. The main output signal is a baseband signal after combination. Blocks implemented on the chip include, mixers, baseband amplifiers, samplers and output buffers. The receiver demonstrates a novel pulsed LO generation circuitry. A synthesized digital block controls the chip.
The fabricated circuit is a 2.2mm x 1mm, baseband processing system-on-chip targeting distributed massive MIMO system. The chip consists of two processors, a standard RISCV processor for control operations and a custom vector processor specific for MIMO processing. Hardware accelerators are used to support digital Rx/Tx front-end of LTE standard. The SoC was implemented to analyse the costs of implementing a distributed MIMO system. To this end we implemented an 8 complex lane vector processor to handle the MIMO processing in real time. Another key area is the synchronization where a lot of optimization has been performed both in algorithm (running on RISCV) and hardware accelerators. The chip also has various peripherals like Timers, UART, SPI master/slave, GPIO, JTAG for flexibility and ease in debugging. Overall we expect very high energy and area efficiency numbers, especially considering that we perform optimizations in algorithm, hardware architecture and also device level using ST-28nm FD-SOI technology.
Contacts : Markus Grözing, Tobias Tannert, Thomas Veigel, Daniel Widmann
emails : firstname.lastname@example.org
In our research project, we develop an ultra high-speed and broadband Digital-to-Analog Converter (DAC) in ST 28 nm CMOS FD-SOI technology for sampling rates up to 128 GS/s and 8 bit nominal resolution.
Communications equipment. The TopSA is an integrated circuit chip which includes critical mmw blocks for standalone measurements. These mmw blocks are bulding blocks for a phased array Transceiver operating at DBAND frequencies. Speciffically, a nine cascaded stages Low Noise Amplifier, a 180 deggress phase shifter, a Variable Gain Amplifier and a calibration Probe Kit (SOLT) are included.
Communications equipment. The TopRxFEM is an integrated circuit chip with four inputs and one output. The chip operates at the DBAND frequencies (130GHz-170GHz). The four input signals are coming from four separate antennas. Each of the input signals are amplified by a separate LNA and then are all combined together by a 4 to 1 passive weasic.com. A programmable phase shifter controls the combined signal's phase from 0 to 360 degrees. Finally, the combined signal is again amplified via a Variable Gain Amplifier. This integrated circuit chip is the front end module (FEM) of a phased array receiver. In addition, in the Rx FEM the following blocks are included; a bandgap reference circuit, a bias current generator, a SPI (Serial Peripheral Interface) and a temperature sensor.
communications equipment. The TopTxFEM is an integrated circuit chip with one input and four outputs. The chip operates at the DBAND frequencies (130GHz-170GHz). The input signal is amplified and then it is split into 4 parallel paths. In each path there is a programmable phase shifter of 0 to 360 degrees. At the end of each path there is a power amplifier in order to drive a separate antenna. At the output of each PA there is an envelope detector which measures the output power. This integrated circuit chip is the front end module (FEM) of a phased array transmitter. Furthermore, the TX FEM includes a bandgap reference circuit along with a bias current generator, SPI (Serial Peripheral Interface) and a temperature detector.
This power management IC is intended for large-scale, resilient, and energy-starved environments. Aside from having two energy harvesting ports, an efficient energy combiner, battery charger, and a 100mW output regulator, it also provides the sensor node with additional data such as harvested energy flow rates, battery and capacitor charge levels, and internal temperature. Energy, voltage, and temperature information is delivered to the sensor node, in addition to the regulated supply voltages from the battery and energy harvesters. This data is intended to be used for sensor node data tagging for resilient operation, as well as easing the burden of adding intelligence at the network, system, and application levels.
This quad N-Channel MOSFET driver is designed to drive MOSFETs in synchronous full-bridge configuration. The gate driver takes a PWM signal from the microcontroller and provides the driving levels to the power stage MOSFETs. Two external resistors program the turn-on and turn-off dead-time delays. In distributed DC/DC, DC/AC, AC/DC systems or multicell multilevel converters, the gate driver can be synchronized in daisy chain configuration. The master gate driver takes a PWM signal from a master control unit to set up the phase shift among all the gate drivers used in the daisy chain. The robust level shift technology operates at high dv/dt while consuming low power and provides clean output transitions
The range of applications of this chip typically covers nuclear physics experiments, but can naturally extend beyond these to reach other domains such as particle physics, medical imaging, astrophysics, etc. A new multi-channel ASIC called FEANICS (Front-End Adaptive gaiN Integrated CircuitS) based on a floating-point Charge Sensitive Amplifier FPCSA architecture. This architecture is based on automatic gain switching during the rise time of the pulse. By default, the CSA is configured in a high gain mode. If the charge exceeds a specific value, the CSA automatically switches to a low gain value. Thanks to this basic principle, one can reach high dynamic range and high energy resolution.
AwaXe_v2 (Athena Warm Asic for the X-ifu Electronics - Version2) is an upgrade of a demonstration performance and technology design for the Warm Front End Electronics (WFEE) of a future X-ray space telescope ATHENA. The main studied part of this ASIC, is an ultra low gain drift LNA (Low Noise Amplifier) for the readout chain of the X-ray Integral Field Unit (X-IFU) instrument of the ATHENA space observatory. This ASIC also includes series bus RS485/I2C for slow control using RadHard by Design digital library, a differential thermometer for high common-mode noise rejection HK and other test vehicules used for radiation effects study. This ASIC is one of the AwaXe and SQmux ASIC families developed at APC for the SQUID/TES readout. This development is funded by CNES and CNRS.Gain drift as low as 300ppm/°C is optained by post-simulation. The input voltage noise is simulated to an uptodate level of 0.7 nV/Hz in the goal bandwidth of 1-6MHz. The non-linearity is better than 1% over the whole dynamic range of 1 Vpp.
AwaXe_v2dot5 (Athena Warm Asic for the X-ifu Electronics - version 2.5) is an upgrade ASIC developed for the Warm Front End Electronics (WFEE) of the future X-ray space telescope ATHENA. This 2.5 version integrates an ultra-low gain-drift LNA (Low Noise Amplifier), a buffer and 8 configurable current sources developed for a breadboard version (Phase A) of the X-IFU (X-ray Integral Field Unit) readout chaine - ATHENA space observatory. This ASIC also includes series bus RS485/I2C for slow control using RadHard by Design digital library and a differential thermometer for high common-mode noise rejection HK (HouseKeepig and Telemetry). This ASIC is one of the AwaXe and SQmux ASIC families developed at APC for the SQUID/TES readout. This development is funded by CNES and CNRS. This chip is developed to demonstrate the readout of one cryogenic multiplexer (Frequency domain SQUID multiplexer in the 1-6 MHz) for the X-IFU instrument.
A new liquid xenon Compton camera, called XEMIS2, is developed to image small animals using 3 gamma imaging. This new prototype is a monolithic liquid xenon cylindrical camera, which totally surrounds the small animal thanks to its 24 cm axial field of view. The 20480 pads of the ionisation chamber are read thanks to a dedicated ASIC called Idef-X. This 32-channel very-front-end electronics delivers an amplified and filtered signal. This signal delivered by the front-end electronics is readout by a specific 32-channel circuit, called XTRACT, in order to deliver the timing and charge of the relevant events. Each channel of XTRACT is auto-triggered, with a memorization the address of the channel triggered but also the memorization of the peak value of the input voltage signal and its time of arrival. The transmission of these informations (amplitude, time and channel numbers) is performed during a reading sequence thanks to an Asynchronous Binary Tree Multiplexer (ATBM). The power consumption of the complet 32-channel circuit is limited to 50mW.
As stated above, several circuits are integrated in this test chip and used as a proof of concept to test the benefits of the ST 28-nm FDSOI CMOS technology in terms of enhanced body effect to improve the linearity of some analog and mixed-signal circuits, such as Voltage-Controlled-Ring Oscillators (VCROs) and their application to designAnalog-to-Digital Converters (ADCs). A a simulated output spectrum of a 2nd-order VCO-based modulator is depicted by showing the linearity improvement.
This Silicon photo-multiplier front-end chip embeds 16 parallel channels featuring energy measurement and time stamping in 3.7x4.3 mm2. Each channel has a dynamic input, ranging from 150fC to 2.7nC charge from photo-detectors. The analogue chain consists of a low noise current mode preamplifier ,an integrator, a gain corrector compensating the photo-multipliers gain variation, a CR-RC shape reducing out band noise and an analogue memory. The arrival time reference is generated by a current mode comparator. The time stamped in each channel is provided by a reference time unit build around a DLL and a coarse time counter running at 80MHz, the time bin size is 25 ps. The readout is continuous and transfers are performed via a multiplexed analogue output for the energy and a serial digital output for the time.
Catiroc1 is a 16-channel front-end ASIC designed to readout photomultiplier tubes (PMTs). The concept of the ASIC is to combine an auto-trigger chip to 16 PMTs to obtain an autonomous macro-cell. The 16 channels are totally independent and the trigger starts the charge and time measurements which are then converted and stored. Only the hit channels are read out. The time measurement is done by a 26-bit counter at 40 MHz and a Time to Amplitude Converter for the fine time, giving a resolution of 200ps RMS. The charge measurement is done by a preamplifier followed by a shaper with variable shaping times. Charge and fine time values are converted by a 10 bit ADC.
presented reconfigurable wireless power transciever can be configured to transmitter (TX) mode and receiver (RX) mode with most of the hardware being reused, reducing the cost and shrinking the system size. With the cross-connected structure in both TX and RX modes, and the adaptive optimum switching timing control, high power efficiency is achieved. Operating at 6.78MHz, a peak total power efficiency of 78.1% is realized when transmission distance is 11mm. The peak output power is 2.7W with a total power efficiency of 62.7%.
emails : email@example.com, or firstname.lastname@example.org
Petiroc2b is a 32-channel front-end ASIC designed to readout Silicon Photomultipliers (SiPM) for particle time-of-flight measurement applications and for any application that requires both time resolution and precise energy measurement.
Usually the desired signal can be restored from the incoming signal. However, the amplitude can be hardly assured to be always constant even though the frequency is more likely to be intact due to the imperfection of the real world. This is why we need an automatic gain control circuit. Different functional blocks are designed and implemented in the chip with different constraints in termes of the frequency, tracking speed, stability.
A first ASIC was developed in the same technology (ams 0.35um). Some improvements in terms of stability, noise, gain and consumption. Are under study . This chip is a one channel ASIC dedicated to test these improvements. It contains two voltage amplifiers and a single-ended to differential signal converter besides a voltage reference and a current generator
The streak imaging approach is the sampling of just a single spatial line of the scene per unit of time, resulting in a spaciotemporal image which can reach a time resolution about 100 times better than the framing mode. Thus, a temporal resolution better than 1 ns can be achieved while the fastest ultrafast video imager offer a temporal resolution around 100 ns. The drawback of a such high bandwith performance is the noise of the system that increases with the cut-off frequency. In the case of a repeatable input signal, we demonstrated that the noise rejection can be adjust independently of the effective bandwith of the system. Moreover, the readout time (a few Hz) is not limiting the event repetition rate.
The proposed architecture improves harmonic rejection without increasing the complexity compared to conventional LNA-first receivers. This 5-path mixer rejects up to the 8th harmonic with only 3 differential gain stages whereas only the 6th harmonic would be rejected with conventional topologies having the same number of amplifier stages. The RF bandwith considered is from 300MHz to 2.4GHz. The even harmonics are removed from the frequency spectrum of eflo(t) thanks to the differential architecture. The other harmonics are rejected about 73dB, 78dB and 67dB for the 3rd, 5th, and 7th harmonics respectively.
The proposed CMOS image sensor consists of variety of functional blocks. The row decoder block performs row-by-row scanning to provide reset, charge transfer, and readout signals to the pixel array. The DRAM controller is a row scanner which sequentially selects a row of pixels to enable their exposure codes refreshment. During sensor readout periods, the pixel array is read out using a correlated double-sampling (CDS) scheme realized by column-based CDS circuits. Before reaching to a column scanner to output the final image data, pixel output signals are digitized to corresponding digital format through an analog-to-digital convertor (ADC) placed in each column. The fabricated image sensor chip contains 192×192 pixels with a pixel pitch size of 17.2- µm and a fill factor of 35.2%. The chip is powered by two separately regulated 3.3V power sources – one supplies for analog circuits and the other for all digital control modules. In a dark environment, the pixel dark current is measured as 1.36 fA. The lowest achievable detection limit of a pixel is 10.8 nW/ cm2. By calculating the mean of the standard deviation of all pixel outputs, the extracted pixel and column fixed-pattern noise (FPN) are 0.19% and 0.26%, respectively. The prototype camera equipped with the proposed CMOS image sensor experimentally demonstrated single-frame pixel-wise coded exposure in both spatial and temporal domains. Operate at 10fps, the image sensor is exposed to scene for long period and improves SNR in recovered images. In each frame, as pixel readout is not required until coded exposure is accomplished, CS are naturally applied during the exposure period and the image sensor follows a conventional reset-exposure-readout operation flow
The TIA and front-end with discrete time signal processing allows 25 GHz BW targetting 40Gb/s performance. Gain-BW limitation of the CMOS process has limited achievabe equalization limited. That is addressed in this work through discrete time integration. An exampe case is shown in the figure at 32 Gb/s.
The main objective of the research program is to provide an entirely new power architecture for future digital LED signage. The new architecture is based on an integrated solution distributed along the LED signage display. The integrated solution takes advantage of recent advances in high frequency power conversion and microelectronics in order to offer a highly efficient and compact solution for this application. This approach has several advantages such as: higher efficiency, compactness, less wiring, simpler heat removal, and no rotational component (fan-less). The novel architecture enables future digital LED signage displays to achieve optimal performance for each individual LED, leading to a highly efficient final product.
We have proposed a novel system integrating a pair of two wavelength laser sources sensitive to oxygenated hemoglobin (HbO) and deoxygenated or reduced hemoglobin (HbR) and one time-gated 25 x 25 SPAD array detector. The detector gating technique for TCSPC allows probing at depth with small source-detector distance by rejecting the large signal from the surface which otherwise restricts the sensitivity of the probe to the vicinity of its tip. The size of each pixel is 24 µm × 24 µm with integrated fast readout interface electronics to achieve sub-nanosecond temporal resolution. The time-gate is synchronized with respect to the laser pulse by means of the on- chip delay line, whose output is propagated through balanced binary trees and serves as the control signal for the frontend of each SPAD pixel.
Some testing reslts are shown here about noise (less than 1.2LSB rms), and differentail non linearity issues (-0.6 to 1.3LSB so no missing code), which are the most critical parameters for our imaging applications.
4 TDCs with 9, 23, 61, and 141 stages have been integrated. The measurements are in accordance with our theoritical models. They prove the ability of the proposed TDC architecture to enhance the time resolution by increasing the number of stages. The measured time resolution of the smallest TDC is 72 ps, while a time resolution of 30 ps (resp. 14 ps) is obtained with the TDC of 23 (resp. 61) stages. This hardware implementation allows us to further evaluate the performance of the proposed TDC and confirm the advantages of the proposed approach. The fabricated circuit size is a 2.9mm x 2.2mm with a core area of 3.3 mm². A dual-in-line (DIL) ceramic package with 40 pads has been used for packaging the chip.
To obtain the fine lateral resolution, we use near-field beam-forming algorithm based on the ISAR systems. The synthetized beamwidth is less than 0.5 degree. To achieve the decent range resolution, in a FMCW radar configuration, a state-of-the-art chirp bandwidth of 62.4GHz at a center frequency of 221.1GHz is generated and efficiently radiated. The level of integration and the bandwidth is the best among all published works.
To maximize energy effiency, the RISC-V processor is implemented at near/sub-threshold supply voltage. This enables operation in the minimum energy point (MEP) of the device. FDSOI’s unique body-biasing capabilities allow to tune the MEP towards any desired operation point. Further, the processor is equipped with a Timing-Error Detection and Correction (EDaC) technique to overcome the large design margins typically encountered at near/sub-threhold supply voltages. Thanks to the EDaC, the device is able to operate at first point of failiure with minimal voltage margin.
The implemented chip provi des a wireless analog-to-digital (A/D) interface for implantable applications. The chip is realized as a mixed-signal design including a time-based analog-to-digital converter, digital signal processing unit, energy harvesting and communication modules
This Silicon photo-multiplier front-end chip embeds 16 parallel channels featuring energy measurement and time stamping in 3.7x4.3 mm2. Each channel has a dynamic input, ranging from 150fC to 2.7nC charge from photo-detectors. The analogue chain consists of a low noise current mode preamplifier, an integrator, a gain corrector compensating the photo-multipliers gain variation, a CR-RC shape reducing out band noise and an analogue memory. The arrival time reference is generated by a current mode comparator. The time stamped in each channel is provided by a three stages integrated TDC (Time to Digital Converter). A reference time unit build around a DLLs and a coarse time counter running at 80MHz provide a time bin size of 25 ps. The readout is continuous and transfers are performed via a multiplexed analogue output for the energy and a serial digital output for the time.
PETIROC2 combines a very fast (GHz) and low-jitter (50 ps) trigger with accurate charge and time measurements. A multiplexed charge output is also available as well as the 32 trigger outputs. An adjustment of the SiPM gain is possible using a channel-by-channel input DAC. The power consumption is 6 mW/channel
The SoC implementation is a voltage converter free design based on three-level voltage stack operating using a single voltage source of 1.8V. The current consumption of SRAMs in the top stack is recycled to sustain the near/sub-threshold operation of logic circuits in the two lower stacks. The chip achieves up to 95% power delivery efficiency with a negligible area overhead. The energy efficiency achieved at near/sub-threshold operation (0.4V) is 35MMACs/mW with a peak performance of 4MMAC/s.
This 2mm x 2mm chip contains 4 different CMOS inverters (500nm length, 2µm/8µm and 8µm/32µm width, with and without ESD protection), also including separate versions of each transistor of the inverters for characterization.
In this chip several thousand ring oscillators have been placed in a matrix-like structure. They are accessible individually. Also, any two of them can be switched on and connected to the input of an odometer to measure the RTN by measuring the change in the phase between the two oscillations filtering at the same time the jitter. In the picture at the right it is possible to see the output of one of the oscillators of the array.
IDeF-X HDBD is a 32 channel low noise (down to 17 el.rms) Application Specific Integrated Circuit. It was developed in order to read out charges coming from CdTe or Silicon Drift Detectors in both polarities (Cathode or Anode). The ASIC is based on the IDeF-X HD architecture, with some new features such as: pile up detector and recovery system, lower noise down to 17 el.rms, bipolarity and reduced charge sharing.
Built-in differential temperature sensors can be used to characterize analog/RF circuits in a contact-less way. The higher the sensibility of the sensor the higher its characterization capabilities, but any offset must be compensated. This sensor allows an offset calibration with a 10 bits control, allowing a precision of 0.02ºC.
The circuit was designed using the MAD200 technology which enables the integration of OxRAM devices as embedded memory. The signal routing is performed by the integrated array periphery and enables the sourcing and sensing with the help of external source measure units. This approach simplifies the circuit design and enables maximum flexibility for read and write operations. Unfortunately, it also introduces larger parasitics which will have an influence on the circuit behavior. This demonstrator will help to evaluate computing in-memory concepts based on varying OxRAM array architectures to get a better understanding of low level design choices on the general performance. Two particular applications which will be explored with this demonstrator are the inference and learning operations of artifical neural networks. These operations show promising performance increases if realized by computing in-memory approaches.
Different cantilever sizes were designed as test structures to measure device matching. The results showed deviations of less than 1% in resonance frequency. The subdicing works fine. Further improved cantilever layouts will be manufactured in a next process run. The application of a magnotostrictive material layer will be performed at the university to yield the delta-E effect.