PLAS (PipeLined Asymmetric SCA) - A compact, deadtimeless 32-channel analog memory

Run reference : A18V15_4 - IC ams 0.18µm CMOS High Voltage 6 ML aH18A6 (datasheet)

A18V15_4 top_PLAS_A

PLAS is multichannel analog memory ASIC with a two stage structure that removes the readout-related deadtime present in typical SCA (Switched Capacitor Array) circuits. It contains a 32-cell SCA for each input channel, with independent triggers, plus eight 192-cell shared SCA channels that store post-trigger samples from actual pulses. This is a first prototype hosting 32 input channels with a sampling frequency of 200 MHz.