low jitter low spurs All digital phase locked loop

Run reference : S65C15_2 - IC STMicroelectronics 65nm Advanced CMOS 7 ML CMOS065 (datasheet)

S65C15_2 eitjun15b

This is a full design of digital phase locked loop based digital to time converter (DTC), single phase detector and Class-D DCO. This design introduces digital techniques working in background to achieve high performance in terms of phase noise and spurs for wireless communication systems with fast frequency locking and the ability to fix the nonlinearities introduced in the DTC by means of predistortion technique.