The fabricated circuit is a 2.2mm x 1mm, baseband processing system-on-chip targeting distributed massive MIMO system. The chip consists of two processors, a standard RISCV processor for control operations and a custom vector processor specific for MIMO processing. Hardware accelerators are used to support digital Rx/Tx front-end of LTE standard. The SoC was implemented to analyse the costs of implementing a distributed MIMO system. To this end we implemented an 8 complex lane vector processor to handle the MIMO processing in real time. Another key area is the synchronization where a lot of optimization has been performed both in algorithm (running on RISCV) and hardware accelerators. The chip also has various peripherals like Timers, UART, SPI master/slave, GPIO, JTAG for flexibility and ease in debugging. Overall we expect very high energy and area efficiency numbers, especially considering that we perform optimizations in algorithm, hardware architecture and also device level using ST-28nm FD-SOI technology.