LIP6/CORIOLIS

Software

LIP6_CoriolisThe team members have expertise in various areas of electrical engineering and computer science and are active on topics, including digital, analog and mixed-signal CMOS modeling, design, security and reliability.

CORIOLIS environment is a set of EDA tools for Placement and Routing (P&R) of digital CMOS circuits, released under the GPL license. CORIOLIS tool chain includes the digital netlist capture STRATUS, as well as the digital placer ETESIAN and the digital router KITE. There are 2 ways to use the CORIOLIS P&R: 1) with the built-in digital standard cell SXLib library, based on symbolic layout (Alliance SXLIB). The result is a symbolic layout of the whole netlist, placed and routed, as can be seen on figures. To further translate the symbolic layout into real layout related to a specific technology process, a translation file is required, that is subject to valid NDA. This file is available for a set of technologies and may be provided by CMP on demand. 2) With a real PDK and standard cell library from a foundry which also requires a valid NDA available through CMP. CORIOLIS may be downloaded at web site https://www-soc.lip6.fr/en/team-cia....

LIP6-1
AM2901 4 bit part of a CPU

LIP6-2
32 bit processor

LIP6-3
MIPS R3000 processor