STMicroelectronics Wafer-level bumping on 300mm, ST 55nm BiCMOS055, ST 65nm CMOS065 and on ST 28nm CMOS28FDSOI processes

STMicroelectronics Wafer-level packaging Copper-pillar Interconnections

TECHNOLOGY CHARACTERISTICS :

Copper pillars are manufactured at wafer-level by STMicroelectronics. This interconnection is composed of an Under Bump Mettalization (UBM), upon which a pillar of copper is grown, a capping of Sn/Ag allows the die to be assembled on a substrate by reflow process. |

STMicroelectronics Wafer-level bumping

|For information related to ST Copper Pillar dimensions please contact CMP personnel.| Accessibility conditions: -* Copper pillar option is available on CMOS28FDSOI and BiCMOS055 MPW and dedicated runs as options. For compatibility with other technologies, please refer to µ-bumps interconnections section below. -* FC44S pad class must be used in the design to be compatible with this option.

APPLICATION AREA :

Single die flip-chip packaging