OPEN 3D Frontside Micro-Bumps post-process

OPEN 3D IRT Nanoelec/LETI-CEA Flip-Chip Packaging Frontside Micro-Bumps post-process

TECHNOLOGY CHARACTERISTICS :

PNG - 419.7 kb Micro-Bumps (also called copper pillars) are manufactured at wafer-level as a post-process within CEA LETI cleanroom. This interconnection is composed of a pillar of copper upon which a Sn/Ag alloy is deposited to ensure electrical contact. This technique allows very fine pitch (down to 50 µm) and offers improved electro migration performances compared to solder bumps.

The process is the following: Seed Layer (or UBM) deposition, Copper electro-deposition (requires masking), Sn/Ag alloy deposition, Seed layer etching and reflow.

This post-process is available for projects and wafers processed through CMP. Guaranteed minimum delivered pieces: 40.

OPEN 3D Micro-Bumps post-process option is available as an MPW on the last CMP runs of the year on selected technologies nodes and are subject to a minimum participation. Diameter and height are set to 25µm/20µm with a 50 µm minimum pitch. Compatible technologies are: ams C35B4M3, ST CMOS065, ST CMOS028, ST BiCMOS9MW, ST BiCMOS055.

Dedicated run for OPEN3D Micro-Bumps post-process are available on any CMP runs (upon feasibility study). Diameter/height pair is not imposed and can be chosen within process window.

OPEN 3D post-process must be anticipated at an early stage of the project as they require an additional NDA, the distribution a specific DRM and an add-on to the Design-Kit. You must indicate it in the reservation form.

APPLICATION AREA :

3D/2.5D integration

DESIGN KIT VERSION :

CMP/LETI 3D add-on is required to design post-processed modules. Please refer to the data sheet for more information.

Verification tools :

DRC calibre die-level; DRC calibre 3Dstack for assembly-level checks (at CMP only)

LIBRARIES :

3D modules Library