OPEN 3D Backside post-process (TSV, RDL & Bumps)

OPEN 3D IRT Nanoelec/LETI-CEA Wafer-level packaging Backside post-process (TSV, RDL & Bumps)


PNG - 173.1 kb Backside post-process is composed of three modules: Through Silicon Vias (TSV), RDL and Bumps. TSV allow electrical connection between the first metal layer of the wafer frontside and its backside. The thick copper Redirection layer (RDL) allow signal routing on wafer backside. Backside bumps interconnect allow flip-chip assembly.

The backside process is operated at wafer-level as a post-process within CEA LETI cleanroom. TSV manufacturing requires thinning wafer down to a silicon thickness of 120 µm.

This post-process is available for projects and wafers processed through CMP. Guaranteed minimum delivered pieces: 40.

OPEN 3D backside post-process option is available as an MPW on the last CMP runs of the year on selected technologies nodes and are subject to a minimum participation. TSV diameter and depth are set to 60µm/120µm with a 120 µm minimum pitch. Backside RDL is a 4-8 µm thick copper with a minimum width of 20 µm and minimum pitch of 40 µm. Backside bumps diameter and height are set to 65µm/60-70 µm with a 120 µm minimum pitch. Compatible technologies are: ams C35B4M3, ST CMOS065, ST BiCMOS9MW, ST BiCMOS055.

Dedicated run for OPEN3D backside post-process are available on any CMP runs (upon feasibility study). Geometrical parameters are not imposed and can be chosen within process window.

OPEN 3D post-process must be anticipated at an early stage of the project as they require an additional NDA, the distribution a specific DRM and an add-on to the Design-Kit. You must indicate it in the reservation form.


3D/2.5D integration


CMP/LETI 3D add-on is required to design post-processed modules. Please refer to the data sheet for more information.

Verification tools :

DRC calibre die-level; DRC calibre 3Dstack for assembly-level checks (at CMP only)


3D modules Library