MEMS Bulk Micromachining Frontside Bulk Micromachining

MEMS ams Bulk Micromachining CMOS FS Bulk Micromachining 4 ML Frontside Bulk Micromachining


ams 0.35µ processes
Process cross section
Thick Metal module instead of Metal 4 module and with MIM capacitor module
Poly layer(s): 2, high resistive poly
Maximum die size: 2cm x 2cm
DLP Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3.3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C.
Supply voltage: 5V or 3.3V
Die size: Minimum charge of 3 mm².


0.35 µm CMOS process from ams + TMAH post process etching No additional mask for the MEMS post process


MEMS, micromechanics, MOEMS.


4.10, 3.80

Frontend Backend tools :

Cadence IC 6.1.6 Cadence IC 5.1.41_USR6

Simulation tools :

Spectre, Hspice, Ultrasim, NC-Sim, ams-Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys)

Verification tools :

Calibre (Mentor Graphics) + (diva + assura)

Parasitics extraction tools :

PEX (Cadence)

Place route tools :

Encounter Digital Implementation (EDI) (Cadence)


LV Digital standard cells and IO Libraries: CORELIB: General purpose digital library CORELIB_3B: Same as CORELIB with 3 busses (VDD, VSS, GND) IOLIB: IO pads (input, output, bidir). 3.3V and 5V available IOLIBC_3B: Core limited digital IO Libraries Core and IO cells are characterized for 1.8V, 2.2V, 2.7V, 3.3V. Analog standard cells Libraries: IOLIB_ANA: Analog IO pads library IOLIBC_ANA_3B: Core limited Analog IO pads library IOLIB_ANA_HV: High Voltage Analog IO pads library A_CELLS: Analog Library


Typical leadtime: 14-16 weeks from MPW run deadline to to packaged parts
From Q3/2017 to Q2/2018: Exceptional delayed leadtime: 20-22 weeks from MPW run deadline to to packaged parts