IC 28nm CMOS28FDSOI

IC STMicroelectronics 28nm Advanced CMOS FDSOI 8 ML CMOS28FDSOI

TECHNOLOGY CHARACTERISTICS :

CMOS gate length: 28nm drawn poly length
Triple well Fully Depleted SOI devices, with ultrathin BOX and Ground Plane
Body biasing
Dual Vt MOS transistors (LVT, RVT)
Dual gate oxide (1.0V for core and 1.8V for IO)
Temperature range: -40°C to 175°C
Dual-damascene copper for interconnect, low-k dielectric
8 metal layers (8ML) for interconnect
2 thick Cu top metal (0.880 micron)
Low k inter-level dielectric
Fringe MoM capacitors
Inductors
Analog / RF capabilities
Various power supplies supported: 1.8V, 1.0V
Standard cell libraries (more than 3Mgates/mm2)
Embedded memory (Single port RAM / ROM / Dual Port RAM).

Introduction to FD-SOI video

APPLICATION AREA :

Internet of Things, Wearable • Ultra-low-voltage operation • FBB optimizes power/performance • Efficient RF and analog integration Automotive • Well-managed leakage in high-temperature environments • High reliability thanks to highly-efficient memories Networking Infrastructure • Energy-efficient multicore • Adapt performance & power to workload via FBB • Excellent performance in memories Consumer Multimedia • Optimized SoC integration (Mixed-signal & RF) • Energy-efficient SoC under all thermal conditions • Optimized leakage in idle mode

DESIGN KIT VERSION :

1.2

Frontend Backend tools :

Cadence IC 6.1.7

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight)

Verification tools :

Calibre (Mentor Graphics) PVS (Cadence)

Parasitics extraction tools :

StarRCXT (Synopsys), QRC (Cadence)

Place route tools :

Innovus (Cadence), ICC (Synopsys)

LIBRARIES :

CORE cells Libraries: - CORE: General purpose core cells - CLOCK: Buffer cells for clock tree synthesis - PR: Place and route filler cells IO cells Libraries: - 1.8V Digital IOs - 1.0V, 1.8V, 3.3V Analog IOs - Body Bias supply pads - Bonding pads and Flip-Chip pads On request: - SHIFT: Level Shifters libraries - CORI: Isolation cells - CORR: Retention cells - Compensation cells - DLL, PLL.

TURNAROUND TIME :

Typical leadtime: 24-32 weeks from MPW run deadline to packaged parts