IC 130nm HCMOS9A

IC STMicroelectronics 130nm CMOS High Voltage 4 ML HCMOS9A

TECHNOLOGY CHARACTERISTICS :

CMOS gate length: 130nm drawnpoly length
Deep Nwell and Deep Trench Isolation
Vt transistor offering (Low Power, Analog)
Threshold voltages (for 2 families above): VTN = 700/697mV, VTP = 590/626mV
Isat (for 2 families above): TN: 280/658uA/um - TP: 104/333uA/um
Bipolar NPN transistors
Typical beta: 90 Ft Max @ Vbc=0: 2,4GHz
2 specific implant levels: NDRIFT & PDRIFT MIM 5fF/µm2
Double gate oxide for analog features
Temperature range: -40°C to 175°C
4 metal layers in standard Fluorinated SiO2 Inter Metal dielectrics
Power supply: 1. 2V for Digital, 4.6V for Analog application Multiple
Standard cell libraries.

DESIGN KIT VERSION :

10.9

Frontend Backend tools :

Cadence IC 6.1.7

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)

Verification tools :

Calibre (Mentor Graphics) PVS (Cadence)

Parasitics extraction tools :

StarRCXT (Synopsys), QRC (Cadence)

Place route tools :

Innovus (Cadence)

LIBRARIES :

CORE cells Libraries:
 CORE: General purpose core libraries
 CORX: Complementary core libraries (complex gates).
 PR: Place and route filler cells
IO cells Libraries:
 1.2V, 1.8V, 4.6V, 20V IO pads, Digital and Analog
 bonding pads and flip-chip pads.
On request:
 Level Shifters.

TURNAROUND TIME :

Typical leadtime: 16-18 weeks from MPW run deadline to packaged parts