CMOS Gate length: 130nm drawn, 130nm effective
Deep Nwell and Deep Trench Isolation
Double Vt transistor offering (Low Leakage , High Speed)
Dual gate oxide (1.2V for core and 2.5V for IO)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic
TP @ 1.2V: 240/310uA/mic
Bipolar SiGe transistors: High Speed NPN
Medium VoltageNPN
Typical beta (for 2 families above): 1000/1000
Typical Ft (for 2 families above): 230/150GHz
Power supply 1.2V
Temperature range: -40°C to 175°C 6 Cu metal layers
Low k inter-level dielectric
MIM capacitors
Standard cell libraries (more than 180kgates/mm2)
Embedded memory (Single port RAM / ROM / dual port RAM).
2.9.b
Cadence IC 6.1.6
Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS GoldenGate (Keysight)
Calibre (Mentor Graphics) PVS (Cadence)
StarRCXT (Synopsys), QRC (Cadence)
Innovus (Cadence), ICC (Synopsys)
CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CLOCK: Buffer cells for clock tree synthesis - PR: Place and route filler cells + IO cells Libraries: - 2.5V, 3.3V IO pads, Digital and Analog – bonding pads and flip-chip pads. On request: - Level Shifters - LVDS Pads - DLL, PLL - …
Typical leadtime: 16-18 weeks from MPW run deadline to packaged parts