IC 0.35µm S35D4M5

IC ams 0.35µm BiCMOS SiGe 4 ML S35D4M5


SiGe BiCMOS 0.35 S35D4M5 from ams
Met. layer(s): 4, thick metal
MIM capacitor Poly layer(s): 2, high resistive poly.
Maximum die size: 2cm x 2cm
Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C.
Supply voltage: 5V or 3.3V.


High performance analog/RF/digital process


Mixed signal analog/RF/digital, large digital designs, system on chip


4.10 ISR 15

Frontend Backend tools :

Cadence IC 6.1.6

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)

Verification tools :

Assura (Cadence), Calibre (Mentor Graphics)

Parasitics extraction tools :

QRC (Cadence)

Place route tools :

Encounter Digital Implementation (Cadence)


Analog libraries:

  • A_CELLS: Low Voltage Analog Standard Cells
  • ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices
  • IOLIB_ANA*: Analog I/O pads & Power Supply Pads
  • IOLIBC_ANA*: Core Limited Analog I/O pads & Power Supply Pads
  • IOLIB*_ANA_3B*: 3-Bus Analog I/O pads & Power Supply Pads
  • RFPADS_4M, RFPADS_3B_4M: RF Pads
  • SPIRALS_4M, SPIRALSD_4M: Inductors

Digital libraries:

  • CORELIB*: 3.3V Digital Standard Cells
  • CORELIB_V5*: 5V Digital Standard Cells
  • CORELIB*_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND)
  • CORELIBD*: Dense 3.3V Digital Standard Cells
  • IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads
  • IOLIBC*: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads
  • IOLIB*_V5*: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply
  • IOLIB*_3B*: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads


Typical leadtime: 10-12 weeks from MPW run deadline to packaged parts
In 2018, AMS runs faced unexpected long lead-times. Starting from Q1 2019, lead-times are back to standard ones.