IC 0.35µm H35B4D3

IC ams 0.35µm CMOS High Voltage 4 ML H35B4D3


Met. layer(s): 4
Thick Metal 4
Poly layer(s): 2, high resistive poly
Maximum die size: 2cm x 2cm
Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters.
Floating digital pads available with 3.3V
Temp. range: -40° C. / +125° C.
Supply voltage: 5V, 3.3V, 20V, 50V, Max operating voltage 120V (max gate voltage 5V, 20V).


High performance analog/digital/HV process ?


Mixed signal analog digital, HV designs, system on chip


4.10, 3.80

Frontend Backend tools :

Cadence IC 6.1.5 Cadence IC 5.1.41_USR6

Simulation tools :

Spectre, Hspice, Ultrasim, NC-Sim, ams-Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys)

Verification tools :

Assura, PVS (Cadence) Calibre (Mentor Graphics)

Parasitics extraction tools :

QRC (Cadence) Calibre xRC (Mentor Graphics)

Place route tools :

Encounter Digital Implementation (EDI) (Cadence)


LV Digital standard cells and IO Libraries: - CORELIB: General purpose digital library - CORELIB_3B: Same as CORELIB with 3 busses (VDD, VSS, GND) - IOLIB: IO pads (input, output, bidir). 3.3V and 5V available - IOLIBC_3B: Core limited digital IO Libraries - Core and IO cells are characterized for 1.8V, 2.2V, 2.7V, 3.3V. Analog standard cells Libraries: - IOLIB_ANA: Analog IO pads library - IOLIBC_ANA_3B: Core limited Analog IO pads library - IOLIB_ANA_HV: High Voltage Analog IO pads library - A_CELLS: Analog Library HV Digital standard cells and IO Libraries: - CORELIB_HV : CORELIB for high voltage. - IOLIB_HV : High Voltage digital IO pads library


Typical leadtime: 10-12 weeks from MPW run deadline to packaged parts
From Q3/2017 to Q2/2018: Exceptional delayed leadtime: 16-18 weeks from MPW run deadline to to packaged parts