IC ON Semiconductor 0.35µm CMOS 4 ML ONC35U
TECHNOLOGY CHARACTERISTICS:
Met. layer(s): 4, thick top metal
Poly layer(s): 2
Maximum die size: : stitching options for larger dies
Available I/O: I/O standard cell libraries for core and pad limited designs, 5V tolerant
Temp. range: -40°C/+150°C
Supply voltage: 3.3V/5V memory options:
- Asynchronous single port SRAM
- Asynchronous dual port SRAM
- Asynchronous diffusion ROM
- EEPROM
SPECIAL FEATURES:
0.35µm base line technology including analog options
- 3 and 5 metal layers options (thick top metal)
- stitching available under request
- Additional options under request: HIPO, MiM Capacitor, Epi
APPLICATION AREA:
Mixed signal designs requiring a moderate amount of digital logic (up to 250k gates)
DESIGN KIT VERSION:
1.42p2 (Jul.-20)
FRONTEND BACKEND TOOLS:
Cadence IC 6.1.7
SIMULATION TOOLS:
Analog simulations: Spectre (Cadence), Eldo (Mentor Graphics – Siemens EDA), Hspice (Synopsys) Digital simulations: Incisive (Cadence)
VERIFICATION TOOLS:
Calibre (Mentor Graphics – Siemens EDA)
PARASITICS EXTRACTION TOOLS:
Calibre xRC (Mentor Graphics – Siemens EDA)
PLACE ROUTE TOOLS:
Synopsys Apollo, Astro and Cadence Silicon Ensemble
LIBRARIES:
For standard cell :
- ultra high density core cell
- mixed-signal core cell – separate substrate for reduced noise
- 5V capable core cell – thick gate logic design
- core cell level shifters
For standard I/O :
- fat pad I/O library (for core limited designs)
- tall pad I/O library (for pad limited designs)
- 5V capable I/O library – thick gate logic design
TURNAROUND TIME:
18 weeks
