IC 0.35µm CMOS HV ONC35I3T50U

IC ON Semiconductor 0.35µm CMOS High Voltage 4 ML ONC35I3T50U


Met. layer(s): 4, thick top metal
Poly layer(s): 1
Available I/O: I/O standard cell libraries for core and pad limited designs, 5V tolerant
Temp. range: -40°C/+190°C
High Voltage devices: up to 40V
Digital and analog supply voltage: 3.3V


LOCOS isolation for CMOS and Deep Trench Isolation for High voltage
Extended temperature range (-40°C/+190°C)


Answer to the need for increased digital content in a mixed signal and/or high voltage environment
3 and 5 metal layers options (thick top metal)
Additional options on request: MiM capacitor, HIPO, Polyimide


Cadence 5, Cadence 6 and Mentor Pyxis

Frontend Backend tools :

Synopsys Design Compiler and Cadence Verilog (for digital design); Cadence DFII (4.4.6) and Spectre (for analog design)

Simulation tools :

Spectre, Eldo and HSpice (analog simulation)

Verification tools :

Mentor Calibre

Parasitics extraction tools :

Calibre PEX

Place route tools :

Synopsys Apollo and Cadence Silicon Ensemble


For standard cell :

  • ultra high density core shell

For standard I/O :

  • 5V capable fat pad I/O library (for core limited designs)
  • 5V capable tall pad I/O library (for pad limited designs)
  • fat pad I/O library (for core limited designs)
  • tall pad I/O library (for pad limited designs)

Memory options

Synchronous high speed/high temp single port SRAM
Synchronous high speed/high temp dual port SRAM
Low power synchronous SRAM
Synchronous high speed/high temp diffusion ROM
Low power synchronous via programmable ROM
One-Time Programmable (OTP)
EEPROM (no additional masks or processing steps)


15 weeks