Met. layer(s): 4, thick top metal
Poly layer(s) : 2
Available I/O : I/O standard cell libraries for core and pad limited designs
Temp. range : -40°C/+155°C
Supply voltage : 3.3V/12V
25V HV technology
Answer to the need for increased digital content in a mixed signal and/or high voltage environment
3 and 5 metal layers options (thick top metal)
Additional options on request: HIPO, MiM capacitor, Epi
Cadence 5
Synopsys Design Compiler and Cadence Verilog(for digital design);Cadence DFII(4.4.6) and Spectre(for analog design)
Spectre,Eldo and HSpice (analog simulation)
Mentor Calibre
Synopsys Apollo and Cadence Silicon Ensemble
For standard cell :
ultra high density core shell
core cell level shifters
For standard I/O :
fat pad I/O library (for core limited designs)
tall pad I/O library (for pad limited designs)
Synchronous high speed/high temp single port SRAM
Synchronous high speed/high temp dual port SRAM
Low power synchronous SRAM
Synchronous high speed/high temp diffusion ROM
Low power synchronous via programmable ROM
One-Time Programmable (OTP)
EEPROM (no additional masks or processing steps)
18 weeks