IC 0.35µm CMOS HV ONC35-I3T50U

IC ON Semiconductor 0.35µm CMOS High Voltage 4 ML ONC35I3T50U

TECHNOLOGY CHARACTERISTICS:

Met. layer(s): 4, thick top metal
Poly layer(s): 1
Available I/O: I/O standard cell libraries for core and pad limited designs, 5V tolerant
Temp. range: -40°C/+190°C
High Voltage devices: up to 40V
Digital and analog supply voltage: 3.3V

SPECIAL FEATURES:

LOCOS isolation for CMOS and Deep Trench Isolation for High voltage
Extended temperature range (-40°C/+190°C)

APPLICATION AREA:

Answer to the need for increased digital content in a mixed signal and/or high voltage environment
3 and 5 metal layers options (thick top metal)
Additional options on request: MiM capacitor, HIPO, Polyimide

DESIGN KIT VERSION:

1.5 (Jul.-20)

FRONTEND BACKEND TOOLS:

Cadence IC 6.1.7

SIMULATION TOOLS:

Analog simulations: Spectre (Cadence), Eldo (Mentor Graphics – Siemens EDA), Hspice (Synopsys) Digital simulations: Incisive (Cadence)

VERIFICATION TOOLS:

Calibre (Mentor Graphics – Siemens EDA)

PARASITICS EXTRACTION TOOLS:

Calibre xRC (Mentor Graphics – Siemens EDA)

PLACE ROUTE TOOLS:

Synopsys Apollo and Cadence Silicon Ensemble

LIBRARIES:

For standard cell :

• ultra high density core shell

For standard I/O :

• 5V capable fat pad I/O library (for core limited designs)
• 5V capable tall pad I/O library (for pad limited designs)
• fat pad I/O library (for core limited designs)
• tall pad I/O library (for pad limited designs)

Memory options

Synchronous high speed/high temp single port SRAM
Synchronous high speed/high temp dual port SRAM
Low power synchronous SRAM
Synchronous high speed/high temp diffusion ROM
Low power synchronous via programmable ROM
One-Time Programmable (OTP)
EEPROM (no additional masks or processing steps)

TURNAROUND TIME:

15 weeks