This 0.35 CMOS-Opto process is offered in each 0.35 CMOS run (C35B4C3).
This is a ARC (Anti Reflective Coating) option.
The C35B4O1 is with 4 layers metal available for prototyping and low volume production.
Met. layer(s): 4
Poly layer(s): 2
Maximum die size: 2cm x 2cm
DLP Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C.
Supply voltage: 5V or 3.3V.
High performance analog/digital process + anti-reflective coating for optical devices
Provides enhanced optical sensitivity for embedded photodiodes and high density CMOS camera products.
4.10 ISR 15 (Nov.-17)
Cadence IC 6.1.6
Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)
Assura (Cadence), Calibre (Mentor Graphics)
QRC (Cadence)
Encounter Digital Implementation (Cadence)
Analog libraries: -* A_CELLS: Low Voltage Analog Standard Cells -* ESDLIB, PRIMLIB, PRIMLIBRF: Primitive Devices -* IOLIB_ANA*: Analog I/O pads & Power Supply Pads -* IOLIBC_ANA*: Core Limited Analog I/O pads & Power Supply Pads -* IOLIB*_ANA_3B*: 3-Bus Analog I/O pads & Power Supply Pads -* SPIRALS_4M, SPIRALSD_4M : Inductors Digital libraries: -* CORELIB*: 3.3V Digital Standard Cells -* CORELIB_V5*: 5V Digital Standard Cells -* CORELIB*_3B: Digital Standard Cells with 3 Busses (VDD, VSS, GND) -* CORELIBD*: Dense 3.3V Digital Standard Cells -* IOLIB_4M: Digital Input/Output/Bidirectional buffers & Power Pads -* IOLIBC*: Core Limited Digital Input/Output/Bidirectional buffers & Power Pads -* IOLIB*_V5*: Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply -* IOLIB*_3B*: 3-Bus Digital Input/Output/Bidirectional buffers & Power Pads
Typical leadtime: 10-12 weeks from MPW run deadline to packaged parts