This 0.35 CMOS-Opto process is offered in each 0.35 CMOS run (C35B4C3).
This is a ARC (Anti Reflective Coating) option.
The C35B4O1 is with 4 layers metal available for prototyping and low volume production.
Met. layer(s): 4
Poly layer(s): 2
Maximum die size: 2cm x 2cm
DLP Usable cells: about 300 digital cells
Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters
Temp. range: -40° C. / +125° C.
Supply voltage: 5V or 3.3V.
Provides enhanced optical sensitivity for embedded photodiodes and high density CMOS camera products.
4.10, 3.80
Cadence IC 6.1.5 Cadence IC 5.1.41_USR6
Spectre, Hspice, Ultrasim, NC-Sim, ams-Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys)
Assura, PVS (Cadence) Calibre (Mentor Graphics)
QRC (Cadence) Calibre xRC (Mentor Graphics)
Encounter Digital Implementation (EDI) (Cadence)
LV Digital standard cells and IO Libraries: - CORELIB: General purpose digital library - CORELIB_3B: Same as CORELIB with 3 busses (VDD, VSS, GND) - IOLIB: IO pads (input, output, bidir). 3.3V and 5V available - IOLIBC_3B: Core limited digital IO Libraries - Core and IO cells are characterized for 1.8V, 2.2V, 2.7V, 3.3V. Analog standard cells Libraries: - IOLIB_ANA: Analog IO pads library - IOLIBC_ANA_3B: Core limited Analog IO pads library - IOLIB_ANA_HV: High Voltage Analog IO pads library - A_CELLS: Analog Library
Typical leadtime: 10-12 weeks from MPW run deadline to packaged parts
From Q3/2017 to Q2/2018: Exceptional delayed leadtime: 16-18 weeks from MPW run deadline to to packaged parts
