IC 0.18µm CMOS ONC18MS

IC ON Semiconductor 0.18µm CMOS 5 ML ONC18MS


Met. layer(s): 5, thick top metal
Poly layer(s): 1
Maximum die size: stitching options for larger dies
Available I/O: I/O standard cell libraries for core and pad limited designs, with internal level shifters, for various voltages
Temp. range: -45°C/+135°C
Supply voltage: 1.8V/3.3V Memory options:

  • single port SRAM
  • dual port SRAM
  • ROM
  • non-volatile memory
  • One-Time Programmable (OTP)


Digital, mixed signal 0.18µm base line technology

  • 4 and 6 metal layers options (thick top metal)
  • stitching available under request
  • Additional options on request: High Vt, Deep N Well, Single MiM capacitor, Stacked CS MiM capacitor, PPHR (High resistive poly resistor), ESD implant, LTC (Low Temp. Coefficient Resistor), Targeted native devices, Zener diode, NPR (RN poly resistor), Linear MOSCAP, Planar passivation


Highly integrated high voltage mixed signal processes ideal for many automotive, industrial, medical and defense applications


1.32p2 (Dec.-19)

Frontend Backend tools :

Cadence IC 6.1.7

Simulation tools :

Cadence Incisive and Mentor Questa for digital simulation ; Cadence Spectre-AP-UltraSim, Mentor IC Analyst and Mentor Eldo-Eldo Premier-Adit for analog simulation

Verification tools :

Mentor Calibre

Parasitics extraction tools :

Mentor Calibre xRC-PEX (for analog parasitic extraction) and Synopsys StarRC (for digital parasitic extraction)

Place route tools :

Cadence Encounter, Mentor Olympus-SOC and Synopsys IC Compiler for digital design ; Cadence VSR (CCAR, VCR) and Mentor iroute-Pyxis Custom Router for analog mixed signal design


Standard core cell library:

  • 1.8V standard core cell
  • 1.8V low leakage core cell
  • 3.3V high voltage core cell
  • evel shifters

I/O library:

  • 1.8V core and pad limited designs, 3V tolerant
  • 2.5V pad limited design, with 1.8V level shifter
  • 3.3V core and pad limited designs, with and without level shifter, 5V tolerant
  • 5V core limited designs


17 weeks