Met. layer(s): 5, thick top metal
Poly layer(s): 1
Maximum die size: stitching options for larger dies
Available I/O: I/O standard cell libraries for core and pad limited designs, with internal level shifters, various voltages
Bipolar transistors: HV and LV Parasitic
High Voltage devices: HV 70V DMOS
Temp. range: -45°C/+200°C
Supply voltage: 1.8V/3.3V
Memory options
High-voltage automotive applications thanks to Deep Trench Isolation (DTI)
Also serves as a platform for highly integrated high voltage mixed signal processes ideal for many industrial applications.
1.32p2 (Dec.-19)
Cadence IC 6.1.7
Cadence Incisive and Mentor Questa for digital simulation ; Cadence Spectre-AP-UltraSim, Mentor IC Analyst and Mentor Eldo-Eldo Premier-Adit for analog simulation
Mentor Calibre
Mentor Calibre xRC-PEX (for analog parasitic extraction) and Synopsys StarRC (for digital parasitic extraction)
Cadence Encounter, Mentor Olympus-SOC and Synopsys IC Compiler for digital design; Cadence VSR (CCAR, VCR) and Mentor iroute-Pyxis Custom Router for analog mixed signal design
Standard core cell library:
I/O library:
21 weeks