IC 0.18µm CMOS HV ONC18I4T

IC ON Semiconductor 0.18µm CMOS High Voltage 5 ML ONC18I4T

TECHNOLOGY CHARACTERISTICS :

Met. layer(s): 5, thick top metal
Poly layer(s): 1
Maximum die size: stitching options for larger dies
Available I/O: I/O standard cell libraries for core and pad limited designs, with internal level shifters, various voltages
Bipolar transistors: HV and LV Parasitic
High Voltage devices: HV 70V DMOS
Temp. range: -45°C/+200°C
Supply voltage: 1.8V/3.3V
Memory options

• single port SRAM
• dual port SRAM
• ROM
• non-volatile memory
• One-Time Programmable (OTP)

SPECIAL FEATURES :

• BCD/HV technology (45V/70V)
• Deep Trench Isolation
• Extended temperature range (-45°C/+200°C)
• 4 and 6 metal layers options (thick top metal)
• stitching available on request
• additional options on request : Deep N Well, Single MiM capacitor, Stacked CS MiM capacitor, PPHR (High resistive poly resistor), ESD implant, LTC (Low T° Coefficient Resistor), Targeted native devices, Zener diode, NPR (RN poly resistor), Linear MOSCAP, Planar passivation

APPLICATION AREA :

High-voltage automotive applications thanks to Deep Trench Isolation (DTI)
Also serves as a platform for highly integrated high voltage mixed signal processes ideal for many industrial applications.

DESIGN KIT VERSION :

1.32p2 (Dec.-19)

Frontend Backend tools :

Cadence IC 6.1.7

Simulation tools :

Cadence Incisive and Mentor Questa for digital simulation ; Cadence Spectre-AP-UltraSim, Mentor IC Analyst and Mentor Eldo-Eldo Premier-Adit for analog simulation

Verification tools :

Mentor Calibre

Parasitics extraction tools :

Mentor Calibre xRC-PEX (for analog parasitic extraction) and Synopsys StarRC (for digital parasitic extraction)

Place route tools :

Cadence Encounter, Mentor Olympus-SOC and Synopsys IC Compiler for digital design; Cadence VSR (CCAR, VCR) and Mentor iroute-Pyxis Custom Router for analog mixed signal design

LIBRARIES :

Standard core cell library:

• 1.8V standard core cell
• 1.8V low leakage core cell
• 3.3V high voltage core cell
• level shifter

I/O library:

• 1.8V core and pad limited designs, 3V tolerant
• 2.5V pad limited designs, with 1.8V level shifter
• 3.3V core and pad limited designs, with and without level shifter, 5V tolerant
• 5V core limited design

TURNAROUND TIME :

21 weeks