CMP, in partnership with ams, offers a 2.5D integration solution through specific MPW runs for silicon interposer production, allowing side by side integration of heterogeneous dies with higher interconnection densities than organic substrates, thus promoting package footprint reduction, increased inter-die bandwidth and decreased power consumption.
This interposer offer is based on ams C35B4M3 metal stack (including 4 metal levels for routing), upon which a post-process is performed by an external subcontractor in order to produce a front-side Under Bump Metalization (or UBM) consisting of Ni/Pd/Au stack. For this active interposer offer, Active layers are available for CMOS integration, allowing the implementation of a wide range of functions to the interposer.
The resulting interposer is ready to support flip-chip dies and is compatible with CMP OPEN 3D micro-bumps post-process offer (with a 50 µm min pitch). The interposer includes Wire-bonding pads to allow its connection to a PCB (as chip on board) or a compatible package. Note that this interposer is compatible with OPEN 3D TSV backside post-process.
Access to this silicon interposer offer is based upon a formal DK request as well as administrative and partners approval through our web interface. Interposer run offer is available at any time.
Guaranteed minimum delivered pieces: 40
ams CMOS C35 standard backend: 4 metal layers (3+1 Thick).
Size limit for submitted design is 400 mm2.
For design < 150 mm2, further cost reduction may be applicable under condition.
Active Silicon Si-Interposer for 3D/2.5D integration
ams C35B4 4.10
ams C35B4 libraries