IRT Nanoelec and CMP Announce World’s First Multi-Project Wafer Service with Silicon Photonics on 310nm SOI Platform


IRT Nanoelec, an R&D consortium focused on information and communication technologies (ICT) using micro and nanoelectronics, and CMP, Circuits Multi-Projets®, a service organization in ICs and MEMS prototyping and low volume production, today announced the IC industry’s first multi-project wafer (MPW) process for fabricating silicon-photonics devices on a 310nm silicon on insulator (SOI) platform. The MPW service also includes compatible IC MPW services and the first service for post-process 3D integration on multi-project wafers. IRT, which is headed by CEA-Leti, and CMP announced that service in 2015.

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