STMicroelectronics and CMP organise a two-day training on the ST’s 28nm FDSOI technology.
The first day is an overview of the major analog, digital and RF features of 28nm FDSOI technology. Then follows a focus on the benefits of FD-SOI technology, by taking full advantage of wide voltage range body biasing tuning. For each category of circuits (digital, analog/RF and mmW), concrete presentation and strategy offer are given in order to highlight the main design features specific to FD-SOI and the resulting performances. Then simulations, verification and demos are proposed on the last day.
Tuesday November 20th: (9:30am – 5:45pm)
- Technology Overview
- Analog/RF circuits: benefits of FD-SOI technology
- Technology Presentation: Process Features, Layers & Metal Stack Options
- 28FDSOI strategy offer
- DK structure & Content
Wednesday November 21st: (9:00am – 4:15pm)
- FE Simulation, Model & corner use
- BE Flow, Physical Verification (DRC, LVS)
- BE Flow, Parasitics Extraction (PEX), Post Layout Simulation (PLS)
- With demos.
The registration deadline is October 16th, 2018.
A maximum of attendees is 25 people with a maximum of two persons by Institution.
The registration is free of charge for CMP users but limited for Institutions with NDA in place. Sign-up will be on a first come first serve basis. Attendance is mandatory during these two days.
A CONFIRMATION of your registration will be sent to the email given within next days.
On-line registration form