20-21-Nov-18 - A two-day training on ST’s 28nm FDSOI technology

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STMicroelectronics and CMP organise a two-day training on the ST’s 28nm FDSOI technology.
The first day is an overview of the major analog, digital and RF features of 28nm FDSOI technology. Then follows a focus on the benefits of FD-SOI technology, by taking full advantage of wide voltage range body biasing tuning. For each category of circuits (digital, analog/RF and mmW), concrete presentation and strategy offer are given in order to highlight the main design features specific to FD-SOI and the resulting performances. Then simulations, verification and demos are proposed on the last day.

Agenda

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Tuesday November 20th: (9:30am – 5:45pm)

9:30-10:00 Attendees introduction & expectation
10:00-12:30
including 15mn Break
Technology overview
Lunch
13:30-15:30 Analog/RF circuits: benefits of FD-SOI technology
Break
15:45-16:15 Technology presentation: Process features, layers & Metal stack Options
16:15-16:30 28FDSOI strategy offer
16:30-17:45 DK structure & content

Wednesday November 21st: (9:00am – 4:15pm)

9:00-13:00
including 15mn Break
FE simulation, Model & corner use
BE Flow, Physical verification (DRC, LVS)
Lunch
14:00-15:45 BE Flow, Parasitics Extraction (PEX), Post Layout Simulation (PLS)
With demos
15:45-16:15 Wrap-up session

Registration

The registration is closed.
A maximum of attendees is 25 people with a maximum of two persons by Institution.
The registration is free of charge for CMP users but limited for Institutions with NDA in place. Sign-up will be on a first come first serve basis. Attendance is mandatory during these two days.