STMICROELECTRONICS

IC 28nm CMOS28FDSOI 

TECHNOLOGY CHARACTERISTICS:

CMOS gate length: 28nm drawn poly length
Triple well Fully Depleted SOI devices, with ultrathin BOX and Ground Plane
Body biasing
Dual Vt MOS transistors (LVT, RVT)
Dual gate oxide (1.0V for core and 1.8V for IO)
Temperature range: -40°C to 125°C
Dual-damascene copper for interconnect, low-k dielectric
8 metal layers (8ML) for interconnect
2 thick Cu top metal (0.880 micron)
Low k inter-level dielectric
Fringe MoM capacitors
Inductors
Analog / RF capabilities
Various power supplies supported: 1.8V, 1.0V
Standard cell libraries (more than 3Mgates/mm2)
Embedded memory (Single port RAM / ROM / Dual Port RAM)

APPLICATION AREA:

Internet of Things, Wearable • Ultra-low-voltage operation • FBB optimizes power/performance • Efficient RF and analog integration Automotive • Well-managed leakage in high-temperature environments • High reliability thanks to highly-efficient memories Networking Infrastructure • Energy-efficient multicore • Adapt performance & power to workload via FBB • Excellent performance in memories Consumer Multimedia • Optimized SoC integration (Mixed-signal & RF) • Energy-efficient SoC under all thermal conditions • Optimized leakage in idle mode

DESIGN KIT VERSION:

1.5.a (Sept. 21)

FRONTEND BACKEND TOOLS:

Cadence IC 6.1.7

SIMULATION TOOLS:

Analog simulations: Spectre (Cadence), Eldo (Mentor Graphics – Siemens EDA), ADS for Momentum & GoldenGate (Keysight)
Digital simulation: Xcelium (Cadence)

VERIFICATION TOOLS:

Calibre (Mentor Graphics) PVS (Cadence)

PARASITICS EXTRACTION TOOLS:

StarRCXT (Synopsys), QRC (Cadence)

PLACE ROUTE TOOLS:

Innovus (Cadence), ICC (Synopsys)

LIBRARIES:

CORE cells Libraries: – CORE: General purpose core cells – CLOCK: Buffer cells for clock tree synthesis – PR: Place and route filler cells IO cells Libraries: – 1.8V Digital IOs – 1.0V, 1.8V, 3.3V Analog IOs – Body Bias supply pads – Bonding pads and Flip-Chip pads
On request: – SHIFT: Level Shifters libraries – CORI: Isolation cells – CORR: Retention cells – Compensation cells – DLL, PLL.

TURNAROUND TIME:

Typical leadtime: 24-32 weeks from MPW run deadline to packaged parts

PRICE

STANDARD price in Euro
9000/mm²
Area = X*Y including scribe-line.
Price for Area ≤ 2mm
² with minimum charge of 1.25mm² including scribe-line.
Special additional discount for CNRS Institutions: 1500€/project
18000+[(Area-2) x 6750]/mm²
Price for 2mm² < Area < 10mm² including scribe-line. Contact CMP when Area is larger.

 EP DISCOUNT price in Euro/project
(applied to EUROPRACTICE MEMBERS registered)
1500.

CONTACT 

Support:

Estimate request:

Ask for Design-Kits (DK):
Request form

DOCUMENTATION

Supporting slides:
Andreia Cathelin, ST (Oct. 2016): FDSOI analog Focus
David Jacquet, ST (Oct. 2013): Shanghai SOI Summit
Philippe Flatresse, ST (Sept. 2013): UTBB-FDSOI Design Migration Methodology

Other information:
Press article (Mar. 2018): ASN Outstanding 28nm FD-SOI Chips Taped Out Through CMP by Adele HARS
Announcement (Oct. 2019): Access to ST 28nm FD-SOI in the frame of Nano2022 IPCEI

Trainings

Since 2015, CMP offers several training sessions to the users community. Read more