CMOS Gate length: 130nm drawn, 130nm effective
Deep Nwell and Deep Trench Isolation
Double Vt transistor offering (Low Leakage , High Speed)
Dual gate oxide (1.2V for core and 2.5V for IO)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic
TP @ 1.2V: 240/310uA/mic
Bipolar SiGe transistors: High Speed NPN
Typical beta (for 2 families above): 1000/1000
Typical Ft (for 2 families above): 230/150GHz
Power supply 1.2V
Temperature range: -40°C to 125°C
6 Cu metal layers
Low k inter-level dielectric
Standard cell libraries (more than 180kgates/mm2)
Embedded memory (Single port RAM).
DESIGN KIT VERSION:
FRONTEND BACKEND TOOLS:
Cadence IC 6.1.7
Analog simulations: Spectre (Cadence), Eldo (Mentor Graphics – Siemens EDA), Hspice (Synopsys), ADS for Momentum & GoldenGate (Keysight) Digital simulations: Xcelium (Cadence)
Calibre (Mentor Graphics – Siemens EDA), PVS (Cadence)
PARASITICS EXTRACTION TOOLS:
StarRCXT (Synopsys), QRC (Cadence)
PLACE ROUTE TOOLS:
Innovus (Cadence), ICC (Synopsys)
CORE cells Libraries:
CORE: General purpose core libraries
CLOCK: Buffer cells for clock tree synthesis
PR: Place and route filler cells
IO cells Libraries:
2.5V, 3.3V IO pads, Digital and Analog
bonding pads and flip-chip pads.
Typical leadtime: 16-18 weeks from MPW run deadline to packaged parts
STANDARD price in Euro
Area = X*Y including scribe-line.
Price for Area ≤ 5mm² with minimum charge of 1.25mm² including scribe-line.
Special additional discount for CNRS Institutions: 1500€/project
13000+[(Area-5) x 2200]/mm²
Price for 5mm² < Area < 15mm² including scribe-line. Contact CMP when Area is larger.
EP DISCOUNT price in Euro/project
(applied to (applied to EUROPRACTICE MEMBERS registered) registered)
For all designs without any bipolar transistor, please contact us for pricing.