Gate length : 65nm drawn poly length
Dual or triple Vt MOS transistors Dual or triple gate oxide
Dedicated process flavors for high performance or low power
Dual-damascene copper for interconnect. Low-k (k = 2.9) dielectric.
6 or 7 metal layers dor interconnect.
0.20um metallization pitch.
Analog / RF capabilities.
Various power supplies supported : 2.5V, 1.2V, 1V
Triple standard cell libraries (more than 800kgates/mm2).
Cadence IC 6.1.6
Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight)
Calibre (Mentor Graphics)
Calibre xRC (Mentor Graphics), QRC(Cadence)
Innovus (Cadence), ICC (Synopsys)
CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CLOCK: Buffer cells and the same for clock tree synthesis - PR: Place and route filler cells and the same. On request: - DP: Datapath leaf cells libraries - HD: High density core libraries IO cells Libraries: - 1.8V, 2.5V, 3.3V IO pads: - 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog - Staggered IO pads - Flip-Chip pads - Level Shifters, and compensation cells On request: - LVDS Pads - DLL, PLL - …
Typical leadtime: 22-26 weeks from MPW run deadline to packaged parts