IC 0.18µm aC18A6

IC ams 0.18µm CMOS 6 ML aC18A6

TECHNOLOGY CHARACTERISTICS :

Met. layer(s): 6 metal layers / Thick Metal 6 MiM Capacitors Maximum die size: 2cm x 2cm Standard cells: digital standard cells and IO pads analog standard cells and IO pads
Available I/O: I/O cell library with available for 1.8V/5V.
Temp. range: -40° C. / +180° C.
Supply voltage: 1.8V, 5.0V.

APPLICATION AREA :

Power management applications MEMS and Sensor interfaces Other SOC applications in Medical, Automotive and Industrial High performance mixed analog/digital applications

DESIGN KIT VERSION :

4.14

Frontend Backend tools :

Cadence IC 6.1.6

Simulation tools :

Spectre, Hspice, Ultrasim, NC-Sim, ams-Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys)

Verification tools :

Assura, PVS (Cadence) Calibre (Mentor Graphics)

Parasitics extraction tools :

QRC (Cadence) Calibre xRC (Mentor Graphics)

Place route tools :

Encounter Digital Implementation-EDI- (Cadence)

LIBRARIES :

LV Digital standard cells and IO Libraries: - CORELIB: General purpose digital library - CORELIB_3B: Same as CORELIB with 3 busses (VDD, VSS, GND) - IOLIB: IO pads (input, output, bidir). 3.3V and 5V available - IOLIBC_3B: Core limited digital IO Libraries - Core and IO cells are characterized for 1.8V, 2.2V, 2.7V, 3.3V. Analog standard cells Libraries: - IOLIB_ANA: Analog IO pads library - IOLIBC_ANA_3B: Core limited Analog IO pads library - IOLIB_ANA_HV: High Voltage Analog IO pads library - A_CELLS: Analog Library.

TURNAROUND TIME :

Typical leadtime: 14-16 weeks from MPW run deadline to packaged parts
From Q3/2017 to Q2/2018: Exceptional delayed leadtime: 20-22 weeks from MPW run deadline to to packaged parts